The Modular Modulation Chaotification Map and its Hardware Implementation

The application of chaotic systems is constrained by the prevalence of frail chaos, dynamical degradation, and high costs. To solve these issues, we propose a novel universal modular modulation method for constructing strengthened chaotic systems. First, the chaotic performance of the system is enha...

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Bibliographic Details
Published in:IEEE transactions on instrumentation and measurement Vol. 73; pp. 1 - 9
Main Authors: Liu, Wenhao, Sun, Kehui, Wang, Huihai, Li, Binglun
Format: Journal Article
Language:English
Published: New York IEEE 2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Chaos
Chaos theory
Chaotic mapping
chaotification
Closed loops
Degradation
Effectiveness
Field programmable gate arrays
field-programmable gate array (FPGA)
Logistics
modular modulation
Modulation
Optimization
Parallel processing
parallelism
Pseudorandom
pseudorandom number generator (PRNG)
Random numbers
ISSN:0018-9456, 1557-9662
Online Access:Get full text
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Summary:The application of chaotic systems is constrained by the prevalence of frail chaos, dynamical degradation, and high costs. To solve these issues, we propose a novel universal modular modulation method for constructing strengthened chaotic systems. First, the chaotic performance of the system is enhanced by modulating multiple 1-D seeds together, involving both self-modulation and hybrid-modulation scenarios. Then the results are constrained within a finite range using modular operation, which enhances its chaotic range and traversal. Second, to further improve its anti-degradation ability, the high-dimensional (HD) chaotic system model is established by the closed-loop modulation coupling (CMC) method. Third, we achieve a balance between performance and costs by utilizing simple 1-D functions as seeds and parallel acceleration technique. Theoretical analysis and simulation confirm the effectiveness of this method. The implementation of the field-programmable gate array (FPGA) verifies its cost-effectiveness and parallel acceleration capability. Finally, it is utilized in the pseudorandom number generator (PRNG) to demonstrate its ability to generate high-quality random numbers at a low computing precision.
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ISSN:0018-9456
1557-9662
DOI:10.1109/TIM.2024.3368470