Nile: A Programmable Monitoring Coprocessor

Researchers widely employ hardware performance counters (HPCs) as well as debugging and profiling tools in processors for monitoring different events such as cache hits, cache misses, and branch prediction statistics during the execution of programs. The collected information can be used for power,...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:IEEE computer architecture letters Ročník 17; číslo 1; s. 92 - 95
Hlavní autori: Delshadtehrani, Leila, Eldridge, Schuyler, Canakci, Sadullah, Egele, Manuel, Joshi, Ajay
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.01.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Coprocessors
Cybersecurity
Debugging
Hardware
Hardware coprocessor
Linux
Microprocessors
Monitoring
Pattern matching
Program processors
programmable hardware
RISC
Rockets
shadow stack
Shadows
Software
stack buffer overflow attack
Thermal management
ISSN:1556-6056, 1556-6064
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:Researchers widely employ hardware performance counters (HPCs) as well as debugging and profiling tools in processors for monitoring different events such as cache hits, cache misses, and branch prediction statistics during the execution of programs. The collected information can be used for power, performance, and thermal management of the system as well as detecting anomalies or malicious behavior in the software. However, monitoring new or complex events using HPCs and existing tools is a challenging task because HPCs only provide a fixed pool of raw events to monitor. To address this challenge, we propose the implementation of a programmable hardware monitor in a complete system framework including the hardware monitor architecture and its interface with an in-order single-issue RISC-V processor as well as an operating system. As a proof of concept, we demonstrate how to programmatically implement a shadow stack using our hardware monitor and how the programmed shadow stack detects stack buffer overflow attacks. Our hardware monitor design incurs a 26 percent power overhead and a 15 percent area overhead over an unmodified RISC-V processor. Our programmed shadow stack has less than 3 percent performance overhead in the worst case.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1556-6056
1556-6064
DOI:10.1109/LCA.2017.2784416