An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA

FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mo...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on instrumentation and measurement Jg. 71; S. 1 - 13
Hauptverfasser: Parsakordasiabi, Mojtaba, Vornicu, Ion, Rodriguez-Vazquez, Angel, Carmona-Galan, Ricardo
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Calibration
Carry chains
Clocks
Coders
Converters
dead-time
Delay lines
Field programmable gate arrays
field-programmable gate array (FPGA)
Linearity
multichannel TDCs
Nonlinearity
Propagation delay
Propagation modes
Signal resolution
tapped-delay line (TDL)
time-to-digital converter (TDC)
ISSN:0018-9456, 1557-9662
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mode tapped-delay-line (TDL)-propagating 1's and 0's in alternating measurement cycles-architecture for a field-programmable gate array (FPGA)-based TDC that complies with the mentioned specifications. The dead-time of the proposed TDC is reduced to one system clock cycle by using a toggling input stage and a dual-mode counter-based encoder. To improve the TDC linearity, the TDL sampling sequence is tuned separately for each operating mode. The presented architecture employs a low-resources dual-mode combinatory encoder of one- and zero-counters to remove the bubbles and cover both operating modes. A dual-mode bin-width calibration has been carried out to improve the TDC performance in each mode. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. Experimental results have shown a differential nonlinearity (DNL) within [−0.71 1.05] least significant bit (LSB) and an integral nonlinearity (INL) within [−0.85 0.86] LSB for the propagation of 1's. DNL and INL are within [−0.73 1.06] LSB and [−1.17 0.04] LSB, respectively, for the propagation of 0's. The LSB size is 22.1 ps and the TDC precision is 22.35 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0018-9456
1557-9662
DOI:10.1109/TIM.2021.3136267