An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA
FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mo...
Uloženo v:
| Vydáno v: | IEEE transactions on instrumentation and measurement Ročník 71; s. 1 - 13 |
|---|---|
| Hlavní autoři: | , , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
New York
IEEE
2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Témata: | |
| ISSN: | 0018-9456, 1557-9662 |
| On-line přístup: | Získat plný text |
| Tagy: |
Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
|
| Abstract | FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mode tapped-delay-line (TDL)-propagating 1's and 0's in alternating measurement cycles-architecture for a field-programmable gate array (FPGA)-based TDC that complies with the mentioned specifications. The dead-time of the proposed TDC is reduced to one system clock cycle by using a toggling input stage and a dual-mode counter-based encoder. To improve the TDC linearity, the TDL sampling sequence is tuned separately for each operating mode. The presented architecture employs a low-resources dual-mode combinatory encoder of one- and zero-counters to remove the bubbles and cover both operating modes. A dual-mode bin-width calibration has been carried out to improve the TDC performance in each mode. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. Experimental results have shown a differential nonlinearity (DNL) within [−0.71 1.05] least significant bit (LSB) and an integral nonlinearity (INL) within [−0.85 0.86] LSB for the propagation of 1's. DNL and INL are within [−0.73 1.06] LSB and [−1.17 0.04] LSB, respectively, for the propagation of 0's. The LSB size is 22.1 ps and the TDC precision is 22.35 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article. |
|---|---|
| AbstractList | FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mode tapped-delay-line (TDL)—propagating 1’s and 0’s in alternating measurement cycles—architecture for a field-programmable gate array (FPGA)-based TDC that complies with the mentioned specifications. The dead-time of the proposed TDC is reduced to one system clock cycle by using a toggling input stage and a dual-mode counter-based encoder. To improve the TDC linearity, the TDL sampling sequence is tuned separately for each operating mode. The presented architecture employs a low-resources dual-mode combinatory encoder of one- and zero-counters to remove the bubbles and cover both operating modes. A dual-mode bin-width calibration has been carried out to improve the TDC performance in each mode. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. Experimental results have shown a differential nonlinearity (DNL) within [−0.71 1.05] least significant bit (LSB) and an integral nonlinearity (INL) within [−0.85 0.86] LSB for the propagation of 1’s. DNL and INL are within [−0.73 1.06] LSB and [−1.17 0.04] LSB, respectively, for the propagation of 0’s. The LSB size is 22.1 ps and the TDC precision is 22.35 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article. |
| Author | Parsakordasiabi, Mojtaba Vornicu, Ion Carmona-Galan, Ricardo Rodriguez-Vazquez, Angel |
| Author_xml | – sequence: 1 givenname: Mojtaba orcidid: 0000-0002-4760-3437 surname: Parsakordasiabi fullname: Parsakordasiabi, Mojtaba email: mojtaba@imse-cnm.csic.es organization: Instituto de Microelectrónica de Seville (IMSE-CNM), Consejo Superior de Investigaciones Científicas (CSIC)-Universidad de Seville, Seville, Spain – sequence: 2 givenname: Ion orcidid: 0000-0001-6865-5116 surname: Vornicu fullname: Vornicu, Ion organization: Instituto de Microelectrónica de Seville (IMSE-CNM), Consejo Superior de Investigaciones Científicas (CSIC)-Universidad de Seville, Seville, Spain – sequence: 3 givenname: Angel orcidid: 0000-0002-1006-5241 surname: Rodriguez-Vazquez fullname: Rodriguez-Vazquez, Angel organization: Instituto de Microelectrónica de Seville (IMSE-CNM), Consejo Superior de Investigaciones Científicas (CSIC)-Universidad de Seville, Seville, Spain – sequence: 4 givenname: Ricardo orcidid: 0000-0002-4230-3988 surname: Carmona-Galan fullname: Carmona-Galan, Ricardo organization: Instituto de Microelectrónica de Seville (IMSE-CNM), Consejo Superior de Investigaciones Científicas (CSIC)-Universidad de Seville, Seville, Spain |
| BookMark | eNp9kE1PAjEQhhuDiYjeTbw08Vzsx7ZLj4QvSSAagfOm253VkqWL20Liv3cJxIMHT3OY95l589yijq89IPTAaJ8xqp_X82WfU876ggnFVXqFukzKlGileAd1KWUDohOpbtBtCFtKaaqStItWQ48nZemsAx_xejzCm-D8BzZ4fDAVWdYF4HcI9aGxQFbmeNotIX7WBZ4cTXUwEQrsfJvnA-J3ePo2G96h69JUAe4vs4c208l69EIWr7P5aLgglmsWiUklTXgueVLkVg2AmULmPLGptSKRIEROmeW5KCxQXZZlYXNpNeclWCGMZqKHns539039dYAQs23b07cvM64E00oozduUOqdsU4fQQJlZF010tY-NcVXGaHYSmLUCs5PA7CKwBekfcN-4nWm-_0Mez4gDgN-4VjJhbZMfopZ7EQ |
| CODEN | IEIMAO |
| CitedBy_id | crossref_primary_10_1016_j_nima_2025_170828 crossref_primary_10_1109_TIE_2024_3370941 crossref_primary_10_1109_TIE_2023_3347843 crossref_primary_10_1016_j_nima_2023_168366 crossref_primary_10_1109_TIM_2023_3277958 crossref_primary_10_1109_TCSI_2022_3158022 crossref_primary_10_3390_s25092923 crossref_primary_10_1109_TIM_2024_3509597 crossref_primary_10_1016_j_nima_2025_170201 crossref_primary_10_1109_TIM_2023_3267566 crossref_primary_10_1109_TIM_2024_3472861 crossref_primary_10_1109_TRPMS_2024_3443831 crossref_primary_10_1109_TIM_2024_3398090 crossref_primary_10_1109_TIM_2024_3419091 crossref_primary_10_1109_TIM_2025_3545157 crossref_primary_10_1088_1748_0221_18_07_P07023 crossref_primary_10_3390_s24175512 crossref_primary_10_1016_j_nima_2022_167668 crossref_primary_10_1016_j_measurement_2025_117240 |
| Cites_doi | 10.1109/TIM.2011.2115390 10.1109/NSS/MIC42101.2019.9059958 10.1109/TIM.2017.2663498 10.1109/TNS.2010.2045901 10.1016/j.nima.2013.12.033 10.1016/j.nima.2016.11.031 10.22323/1.370.0094 10.1145/3349801.3357129 10.1109/TIM.2019.2954173 10.1109/APCCAS.2010.5774740 10.1109/TNS.2016.2596305 10.1145/1508128.1508145 10.3390/s19225019 10.1109/I2MTC.2016.7520401 10.1109/JSSC.2013.2259031 10.1109/TIM.2020.2984929 10.1109/I2MTC43012.2020.9129275 10.1109/TNS.2018.2790703 10.1109/TCSII.2017.2698479 10.1109/23.983253 10.24425/mms.2019.130570 10.1016/j.nima.2014.10.040 10.3390/s17040865 10.1109/NSSMIC.2008.4775079 10.1109/TRPMS.2018.2874358 10.1109/4.231325 10.1109/TNS.2015.2475630 10.1109/TIM.2017.2769239 10.1109/TNS.2019.2938571 10.1109/TIE.2018.2842787 10.1109/TNS.2015.2426214 10.1109/TIM.2009.2027777 10.1016/j.nima.2018.02.064 10.1088/0026-1394/41/1/004 10.1109/TNS.2013.2241789 10.1109/RTC.2014.7097544 10.1109/EBCCSP53293.2021.9502401 10.1109/TIM.2020.3036066 10.1109/TBCAS.2018.2865581 10.1109/TNS.2017.2746626 10.1109/TIM.2019.2938436 10.3390/s21010308 10.1109/TNS.2017.2768082 10.1109/TBCAS.2015.2389227 10.1109/TNS.2015.2421319 10.1109/TIM.2018.2880940 10.1109/TNS.2013.2265555 10.1109/ISCAS.2017.8050436 10.1109/TIE.2021.3053905 10.1109/TNS.2017.2705802 10.1109/TIM.2016.2534670 10.1109/FCS.2019.8856004 10.1063/1.5141391 10.1109/TIM.2019.2959423 10.1109/JSSC.2020.3048074 |
| ContentType | Journal Article |
| Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022 |
| Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022 |
| DBID | 97E RIA RIE AAYXX CITATION 7SP 7U5 8FD L7M |
| DOI | 10.1109/TIM.2021.3136267 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005–Present IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Electronics & Communications Abstracts Solid State and Superconductivity Abstracts Technology Research Database Advanced Technologies Database with Aerospace |
| DatabaseTitle | CrossRef Solid State and Superconductivity Abstracts Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts |
| DatabaseTitleList | Solid State and Superconductivity Abstracts |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Physics |
| EISSN | 1557-9662 |
| EndPage | 13 |
| ExternalDocumentID | 10_1109_TIM_2021_3136267 9654192 |
| Genre | orig-research |
| GrantInformation_xml | – fundername: U.S. Office of Naval Research grantid: N00014-19-1-2156 funderid: 10.13039/100000006 – fundername: EU H2020 MSCA through Project ACHIEVE-ITN grantid: 765866 – fundername: Spanish MINECO and European Region Development Fund (ERDF/FEDER) grantid: RTI2018-097088-B-C31 |
| GroupedDBID | -~X 0R~ 29I 4.4 5GY 5VS 6IK 85S 8WZ 97E A6W AAJGR AARMG AASAJ AAWTH ABAZT ABQJQ ABVLG ACGFO ACIWK ACNCT AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD F5P HZ~ H~9 IAAWW IBMZZ ICLAB IDIHD IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P RIA RIE RNS TN5 TWZ VH1 VJK AAYXX CITATION 7SP 7U5 8FD L7M |
| ID | FETCH-LOGICAL-c291t-a75042b524dbc68e1ad5b24c7cc345e33b01c2b3dce09fffdcb5c922fec33a913 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 20 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000761247800086&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 0018-9456 |
| IngestDate | Mon Jun 30 10:13:39 EDT 2025 Tue Nov 18 22:30:38 EST 2025 Sat Nov 29 04:38:17 EST 2025 Wed Aug 27 02:49:15 EDT 2025 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html https://doi.org/10.15223/policy-029 https://doi.org/10.15223/policy-037 |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c291t-a75042b524dbc68e1ad5b24c7cc345e33b01c2b3dce09fffdcb5c922fec33a913 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ORCID | 0000-0002-4760-3437 0000-0001-6865-5116 0000-0002-1006-5241 0000-0002-4230-3988 |
| PQID | 2631963692 |
| PQPubID | 85462 |
| PageCount | 13 |
| ParticipantIDs | proquest_journals_2631963692 crossref_citationtrail_10_1109_TIM_2021_3136267 crossref_primary_10_1109_TIM_2021_3136267 ieee_primary_9654192 |
| PublicationCentury | 2000 |
| PublicationDate | 20220000 2022-00-00 20220101 |
| PublicationDateYYYYMMDD | 2022-01-01 |
| PublicationDate_xml | – year: 2022 text: 20220000 |
| PublicationDecade | 2020 |
| PublicationPlace | New York |
| PublicationPlace_xml | – name: New York |
| PublicationTitle | IEEE transactions on instrumentation and measurement |
| PublicationTitleAbbrev | TIM |
| PublicationYear | 2022 |
| Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | ref13 ref12 ref15 ref14 ref58 ref53 ref52 ref11 ref55 ref10 ref54 ref17 ref16 ref19 ref18 ref51 ref50 (ref57) 2021 ref46 ref45 ref48 ref47 ref42 ref41 ref44 ref43 ref49 ref8 ref7 ref9 ref4 ref3 ref6 ref5 (ref56) 2021 ref35 ref34 ref37 ref36 ref31 ref30 ref33 ref32 ref2 ref1 ref39 ref38 ref24 ref23 ref26 ref25 ref20 ref22 ref28 ref27 ref29 Homulle (ref40) 2015 Kwiatkowski (ref21) 2019; 26 |
| References_xml | – ident: ref8 doi: 10.1109/TIM.2011.2115390 – ident: ref33 doi: 10.1109/NSS/MIC42101.2019.9059958 – ident: ref50 doi: 10.1109/TIM.2017.2663498 – ident: ref42 doi: 10.1109/TNS.2010.2045901 – ident: ref54 doi: 10.1016/j.nima.2013.12.033 – ident: ref53 doi: 10.1016/j.nima.2016.11.031 – ident: ref41 doi: 10.22323/1.370.0094 – volume-title: FPGA Designs for Reconfigurable Converters year: 2015 ident: ref40 – ident: ref9 doi: 10.1145/3349801.3357129 – ident: ref1 doi: 10.1109/TIM.2019.2954173 – ident: ref37 doi: 10.1109/APCCAS.2010.5774740 – ident: ref43 doi: 10.1109/TNS.2016.2596305 – ident: ref52 doi: 10.1145/1508128.1508145 – ident: ref4 doi: 10.3390/s19225019 – ident: ref15 doi: 10.1109/I2MTC.2016.7520401 – ident: ref36 doi: 10.1109/JSSC.2013.2259031 – ident: ref12 doi: 10.1109/TIM.2020.2984929 – ident: ref47 doi: 10.1109/I2MTC43012.2020.9129275 – ident: ref39 doi: 10.1109/TNS.2018.2790703 – ident: ref10 doi: 10.1109/TCSII.2017.2698479 – ident: ref55 doi: 10.1109/23.983253 – volume: 26 start-page: 631 issue: 4 year: 2019 ident: ref21 article-title: Employing FPGA DSP blocks for time-to-digital conversion publication-title: Metrol. Meas. Syst. doi: 10.24425/mms.2019.130570 – ident: ref25 doi: 10.1016/j.nima.2014.10.040 – ident: ref34 doi: 10.3390/s17040865 – ident: ref29 doi: 10.1109/NSSMIC.2008.4775079 – ident: ref6 doi: 10.1109/TRPMS.2018.2874358 – ident: ref24 doi: 10.1109/4.231325 – ident: ref45 doi: 10.1109/TNS.2015.2475630 – ident: ref26 doi: 10.1109/TIM.2017.2769239 – ident: ref31 doi: 10.1109/TNS.2019.2938571 – ident: ref18 doi: 10.1109/TIE.2018.2842787 – volume-title: XEM7310 User’s Manual year: 2021 ident: ref56 – ident: ref20 doi: 10.1109/TNS.2015.2426214 – ident: ref23 doi: 10.1109/TIM.2009.2027777 – ident: ref58 doi: 10.1016/j.nima.2018.02.064 – ident: ref48 doi: 10.1088/0026-1394/41/1/004 – ident: ref5 doi: 10.1109/TNS.2013.2241789 – volume-title: Timing Jitter Tutorial & Measurement Guide year: 2021 ident: ref57 – ident: ref16 doi: 10.1109/RTC.2014.7097544 – ident: ref14 doi: 10.1109/EBCCSP53293.2021.9502401 – ident: ref35 doi: 10.1109/TIM.2020.3036066 – ident: ref3 doi: 10.1109/TBCAS.2018.2865581 – ident: ref46 doi: 10.1109/TNS.2017.2746626 – ident: ref7 doi: 10.1109/TIM.2019.2938436 – ident: ref13 doi: 10.3390/s21010308 – ident: ref19 doi: 10.1109/TNS.2017.2768082 – ident: ref49 doi: 10.1109/TBCAS.2015.2389227 – ident: ref30 doi: 10.1109/TNS.2015.2421319 – ident: ref11 doi: 10.1109/TIM.2018.2880940 – ident: ref44 doi: 10.1109/TNS.2013.2265555 – ident: ref28 doi: 10.1109/ISCAS.2017.8050436 – ident: ref32 doi: 10.1109/TIE.2021.3053905 – ident: ref51 doi: 10.1109/TNS.2017.2705802 – ident: ref38 doi: 10.1109/TIM.2016.2534670 – ident: ref17 doi: 10.1109/FCS.2019.8856004 – ident: ref22 doi: 10.1063/1.5141391 – ident: ref27 doi: 10.1109/TIM.2019.2959423 – ident: ref2 doi: 10.1109/JSSC.2020.3048074 |
| SSID | ssj0007647 |
| Score | 2.4355595 |
| Snippet | FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources.... |
| SourceID | proquest crossref ieee |
| SourceType | Aggregation Database Enrichment Source Index Database Publisher |
| StartPage | 1 |
| SubjectTerms | Calibration Carry chains Clocks Coders Converters dead-time Delay lines Field programmable gate arrays field-programmable gate array (FPGA) Linearity multichannel TDCs Nonlinearity Propagation delay Propagation modes Signal resolution tapped-delay line (TDL) time-to-digital converter (TDC) |
| Title | An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA |
| URI | https://ieeexplore.ieee.org/document/9654192 https://www.proquest.com/docview/2631963692 |
| Volume | 71 |
| WOSCitedRecordID | wos000761247800086&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1557-9662 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0007647 issn: 0018-9456 databaseCode: RIE dateStart: 19630101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3dS8MwED-mKOiD3-J0Sh58EYxr0jZNHsfcVHBDcMLeSpomMNAqbvPvN0k_UBTBp_bhUkp-yeXucvc7gHPDk5xRwnCiucQRNRJzzgTWjEjJSSxNSeJ6n4zHfDoVDy24bGphtNY--UxfuVd_l5-_qqULlXWFa1otrMJdSRJW1mo1WjdhUcmPSewGtlZBfSUZiO7kbmQdQUqsf-rIV5JvR5DvqfJDEfvTZbj9v__aga3KikS9EvZdaOliDza_cAvuwbrP7VTzfXjsFWjgmSLsV9Dkuo98ngCS6Hopn7HrhobqKD5-lC7CgEa-sTQalFzgOkezwspTjosXNHy46R3A03Aw6d_iqpcCVlSQBZaOxp1mMY3yTDGuiczjjEYqUSqMYh2GWUAUzcJc6UAYY3KVxUpQarQKQylIeAirxWuhjwA5t03GhoXKznlmciGsUSXtkwTSWpe8Dd16elNVEY27fhfPqXc4ApFaQFIHSFoB0oaLZsRbSbLxh-y-A6CRq-a-DZ0awbTahfOUMq9gmKDHv486gQ3qyhl8SKUDq4v3pT6FNfWxmM3fz_wC-wSx4Mpk |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3dS8MwED_ED9QHv8X5mQdfBOOatE2Tx-E2FbchbIJvJU0TGMxO3Obfb5J2Q1EEn9qHSyn5JZe7y93vAC4NT3JGCcOJ5hJH1EjMORNYMyIlJ7E0JYlrJ-n1-MuLeFqC60UtjNbaJ5_pG_fq7_LzsZq5UFlduKbVwirclTiKaFBWay30bsKikiGT2C1s7YL5pWQg6oOHrnUFKbEeqqNfSb4dQr6ryg9V7M-X9vb__mwHtio7EjVK4HdhSRd7sPmFXXAP1nx2p5rsQ79RoJbnirBfQYPmLfKZAkii5kyOsOuHhuZxfNyXLsaAur61NGqVbOA6R8PCylOOi1fUfrprHMBzuzW4vcdVNwWsqCBTLB2RO81iGuWZYlwTmccZjVSiVBjFOgyzgCiahbnSgTDG5CqLlaDUaBWGUpDwEJaLcaGPADnHTcaGhcrOeWZyIaxZJe2TBNLal7wG9fn0pqqiGncdL0apdzkCkVpAUgdIWgFSg6vFiLeSZuMP2X0HwEKumvsanM4RTKt9OEkp8yqGCXr8-6gLWL8fdDtp56H3eAIb1BU3-ADLKSxP32f6DFbVx3Q4eT_3i-0TZrzNqw |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=An+Efficient+TDC+Using+a+Dual-Mode+Resource-Saving+Method+Evaluated+in+a+28-nm+FPGA&rft.jtitle=IEEE+transactions+on+instrumentation+and+measurement&rft.au=Parsakordasiabi%2C+Mojtaba&rft.au=Vornicu%2C+Ion&rft.au=Rodriguez-Vazquez%2C+Angel&rft.au=Carmona-Galan%2C+Ricardo&rft.date=2022&rft.pub=IEEE&rft.issn=0018-9456&rft.volume=71&rft.spage=1&rft.epage=13&rft_id=info:doi/10.1109%2FTIM.2021.3136267&rft.externalDocID=9654192 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0018-9456&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0018-9456&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0018-9456&client=summon |