Data Compression Device Based on Modified LZ4 Algorithm

Data compression is commonly used in NAND flash-based solid state drives (SSDs) to increase their storage performance and lifetime as it can reduce the amount of data written to and read from NAND flash memory. Software-based data compression reduces SSD performance significantly and, as such, hardw...

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Bibliographic Details
Published in:IEEE transactions on consumer electronics Vol. 64; no. 1; pp. 110 - 117
Main Authors: Weiqiang Liu, Faqiang Mei, Chenghua Wang, O'Neill, Maire, Swartzlander, Earl E.
Format: Journal Article
Language:English
Published: New York IEEE 01.02.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Compression ratio
Computer architecture
Data compression
Data storage
Dictionaries
Field programmable gate arrays
Flash memories
Flash memory (computers)
FPGA
Hardware
Lempel-Ziv (LZ) algorithms
lossless compression
Lossless equipment
LZ4
Product development
Software algorithms
Solid state devices
solid-state drives (SSDs)
ISSN:0098-3063, 1558-4127
Online Access:Get full text
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Summary:Data compression is commonly used in NAND flash-based solid state drives (SSDs) to increase their storage performance and lifetime as it can reduce the amount of data written to and read from NAND flash memory. Software-based data compression reduces SSD performance significantly and, as such, hardware-based data compression designs are required. This paper studies the latest lossless data compression algorithm, i.e., the Lempel-Ziv (LZ)4 algorithm which is one of the fastest compression algorithms reported to date. A data compression FPGA prototype based on the LZ4 lossless compression algorithm is studied. The original LZ4 compression algorithm is modified for real-time hardware implementation. Two hardware architectures of the modified LZ4 algorithm (MLZ4) are proposed with both compressors and decompressors, which are implemented on an FPGA evaluation kit. The implementation results show that the proposed compressor architecture can achieve a high throughput of up to 1.92 Gb/s with a compression ratio of up to 2.05, which is higher than all previous LZ algorithm designs implemented on FPGAs. The compression device can be used in high-end SSDs to further increase their storage performance and lifetime.
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ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2018.2810480