A Reconfigurable and Pipelined Architecture for Standard-Compatible LDPC and Polar Decoding

With low-density parity-check (LDPC) codes and polar codes selected as the standard codes for the fifth generation (5 G) enhanced Mobile Broad Band scenario (eMBB), a decoding architecture that can simultaneously support the decoding of control and data plane becomes necessary at the terminal side t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on vehicular technology Jg. 70; H. 6; S. 5431 - 5444
Hauptverfasser: Cao, Shan, Lin, Ting, Zhang, Shunqing, Xu, Shugong, Zhang, Chuan
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.06.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
5G mobile communication
Algorithms
Codes
decoder
Decoders
Decoding
Error correcting codes
Hardware
Iterative decoding
Iterative methods
LDPC code
Low density parity check codes
Parity
polar code
Polar codes
reconfigurable architecture
Reconfiguration
standard-compatible
Throughput
ISSN:0018-9545, 1939-9359
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:With low-density parity-check (LDPC) codes and polar codes selected as the standard codes for the fifth generation (5 G) enhanced Mobile Broad Band scenario (eMBB), a decoding architecture that can simultaneously support the decoding of control and data plane becomes necessary at the terminal side to meet the raising requirement for 5 G network deployment. Due to the special structure of LDPC codes according to the Release 15 (R15) 5 G standard, a straight-forward extension of the existing reconfigurable scheme is in general difficult. Therefore in this paper, a unified decoding architecture is proposed that can be reconfigured to either LDPC codes or polar codes. Due to various differences between the two codes such as parity-check matrices, codeword lengths and iterative methods, a joint decoding algorithm is introduced by reordering basic decoding operations to the unified add-comparison-add pattern for both codes. Then, a pipelined structure of reconfigurable decoding unit (RDU) is presented correspondingly which is fully compatible with all decoding patterns of the R15 standard. And finally, a reconfigurable decoder is proposed with multiple levels of parallelism, and the reconfiguration scheme is introduced to improve the hardware utilization and decoding efficiency. The proposed decoder is implemented in FPGA and ASIC, respectively, and has achieved state-of-the-art performance in throughput and area efficiency compared to LDPC-only and polar-only decoders.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0018-9545
1939-9359
DOI:10.1109/TVT.2021.3075232