Parallel Implementation of Model Predictive Control for Multilevel Cascaded H-Bridge STATCOM With Linear Complexity

The algorithm complexity of model predictive control (MPC) for cascaded H-bridge (CHB) static synchronous compensators (STATCOMs) was optimized to a polynomial level in previous studies. However, implementing MPC with conventional approaches still suffers from long execution time, where a low cost d...

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Vydáno v:IEEE transactions on industrial electronics (1982) Ročník 67; číslo 2; s. 832 - 841
Hlavní autoři: Zhang, Yonglei, Yuan, Xibo, Wu, Xiaojie, Yuan, Yalei, Zhou, Juan
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.02.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Accumulators
Algorithm complexity
Algorithms
Automatic voltage control
Capacitors
cascaded H-bridge (CHB)
Classification
Consumption
Digital signal processing
Digital signal processors
Field programmable gate arrays
Microprocessors
model predictive control (MPC)
Optimization
Polynomials
Prediction algorithms
Predictive control
Signal processing algorithms
Sorting algorithms
Static synchronous compensators
static synchronous compensators (STATCOM)
Task complexity
ISSN:0278-0046, 1557-9948
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Shrnutí:The algorithm complexity of model predictive control (MPC) for cascaded H-bridge (CHB) static synchronous compensators (STATCOMs) was optimized to a polynomial level in previous studies. However, implementing MPC with conventional approaches still suffers from long execution time, where a low cost digital signal processor (DSP) is used to execute optimization algorithms and a small-sized field-programmable gate array (FPGA) is used to extend gate signals and sampling functions. This paper presents a parallel implementation approach to reduce the execution time of MPC, where the FPGA is configured to be used for accelerating the high-complexity sorting tasks. By running the DSP and FPGA in parallel, the algorithm execution time is only determined by the DSP, and the resource consumption is only determined by the FPGA. To minimize the resource consumption and requirement in FPGA, a parallel comparison-based sorter with multiple comparison and accumulators is proposed. The proposed implementation method can reduce the time and space complexity of the MPC from the polynomial level to a linear level without additional hardware cost, which means the MPC for medium-voltage CHB STATCOMs (e.g., 20 stages) can be implemented online with existing control platforms. Experimental results for various CHB STATCOMs are presented to validate the proposed configuration and algorithm.
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ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2019.2901647