Multi-objective optimization and visualization for analog design automation

The automated design of analog and mixed-signal circuits is a well-known subject of increasing technical and economical significance, e.g., sensory circuits for internet of things, cyber-physical systems, and Industry 4.0.The demand for rapid solution achievement under constraints, as, e.g., robustn...

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Vydáno v:Complex & intelligent systems Ročník 2; číslo 4; s. 251 - 267
Hlavní autoři: Kammara, Abhaya Chandra, Palanichamy, Lingaselvan, König, Andreas
Médium: Journal Article
Jazyk:angličtina
Vydáno: Berlin/Heidelberg Springer Berlin Heidelberg 01.12.2016
Springer Nature B.V
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ISSN:2199-4536, 2198-6053
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Shrnutí:The automated design of analog and mixed-signal circuits is a well-known subject of increasing technical and economical significance, e.g., sensory circuits for internet of things, cyber-physical systems, and Industry 4.0.The demand for rapid solution achievement under constraints, as, e.g., robustness, in established and emerging technologies as well as the migration between technologies gives incentive to automation activities. Existing approaches and tools still show improvement potential with regard to multi-variate modeling, efficient and multi-objective optimization, as well as transparence and user interaction options during the design. This paper presents new approaches applied within an emerging design environment, denoted as ABSYNTH, with an evolving self-learning architecture for efficient hierarchical optimization in a cascade, which includes function approximators and simulators trained by proven evolutionary optimization algorithms, as well as a novel domain-specific visualization of the optimization space and the trajectory of the design process. Nominal schematic-level sizing of the commonly used Miller, buffer, and folded-cascode amplifier circuits has been studied with our approach. For Miller, buffer, and folded-cascode, a cascade of harmony search and particle swarm optimization on SVR, ngspice, and cadence simulators was found to be roughly 4 times, 2.5 times, and 2.5 times faster, respectively, than the flat approach with equal or better results. In future work, we will improve the approach by including more demanding circuits, statistical deviations, circuit breeding, advanced optimization, and layout generation.
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ISSN:2199-4536
2198-6053
DOI:10.1007/s40747-016-0027-3