DSP design protection in CE through algorithmic transformation based structural obfuscation

Structural obfuscation offers a means to effectively secure through obfuscation the contents of an intellectual property (IP) cores used in an electronic system-on-chip (SoC). In this work a novel structural obfuscation methodology for protecting a digital signal processor (DSP) IP core at the archi...

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Published in:	IEEE transactions on consumer electronics Vol. 63; no. 4; pp. 467 - 476
Main Authors:	Sengupta, Anirban, Roy, Dipanjan, Mohanty, Saraju P., Corcoran, Peter
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.11.2017 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithm design and analysis Algorithms Delays Design optimization Digital signal processing Digital signal processing (DSP) core Digital signal processors Hardware high-level transformation Intellectual property IP networks IP protection Microprocessors Particle swarm optimization Reverse engineering Signal processing algorithms Space exploration structural obfuscation System on chip Transformations
ISSN:	0098-3063, 1558-4127
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Abstract	Structural obfuscation offers a means to effectively secure through obfuscation the contents of an intellectual property (IP) cores used in an electronic system-on-chip (SoC). In this work a novel structural obfuscation methodology for protecting a digital signal processor (DSP) IP core at the architectural synthesis design stage. The proposed approach specifically targets protection of IP cores that involve complex loops. Five different algorithmic level transformation techniques are employed: loop unrolling, loop invariant code motion, tree height reduction/increment, logic transformation and redundant operation removal. Each of these can yield camouflaged functionally equivalent designs. In addition, low cost obfuscated design is generated through proposed approach through the use of multi-stage algorithmic transformation and particle swarm optimization (PSO)-drive design space exploration (DSE). Results of proposed approach yielded an enhancement obfuscation of 22 % and reduction in obfuscated design cost of 55 % compared to similar prior art.
AbstractList	Structural obfuscation offers a means to effectively secure through obfuscation the contents of an intellectual property (IP) cores used in an electronic system-on-chip (SoC). In this work a novel structural obfuscation methodology for protecting a digital signal processor (DSP) IP core at the architectural synthesis design stage. The proposed approach specifically targets protection of IP cores that involve complex loops. Five different algorithmic level transformation techniques are employed: loop unrolling, loop invariant code motion, tree height reduction/increment, logic transformation and redundant operation removal. Each of these can yield camouflaged functionally equivalent designs. In addition, low cost obfuscated design is generated through proposed approach through the use of multi-stage algorithmic transformation and particle swarm optimization (PSO)-drive design space exploration (DSE). Results of proposed approach yielded an enhancement obfuscation of 22 % and reduction in obfuscated design cost of 55 % compared to similar prior art.
Author	Sengupta, Anirban Roy, Dipanjan Mohanty, Saraju P. Corcoran, Peter
Author_xml	– sequence: 1 givenname: Anirban surname: Sengupta fullname: Sengupta, Anirban email: asengupt@iiti.ac.in organization: Discipline of Comput. Sci. & Eng., Indian Inst. of Technol., Indore, Indore, India – sequence: 2 givenname: Dipanjan surname: Roy fullname: Roy, Dipanjan email: phd1501201007@iiti.ac.in organization: Discipline of Comput. Sci. & Eng., Indian Inst. of Technol., Indore, Indore, India – sequence: 3 givenname: Saraju P. surname: Mohanty fullname: Mohanty, Saraju P. email: Saraju.Mohanty@unt.edu organization: Dept. of Comput. Sci., Univ. of North Texas, Denton, TX, USA – sequence: 4 givenname: Peter surname: Corcoran fullname: Corcoran, Peter email: peter.corcoran@nuigalway.ie organization: Coll. of Eng. & Inf., Nat. Univ. of Ireland Galway, Galway, Ireland
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SubjectTerms	Algorithm design and analysis Algorithms Delays Design optimization Digital signal processing Digital signal processing (DSP) core Digital signal processors Hardware high-level transformation Intellectual property IP networks IP protection Microprocessors Particle swarm optimization Reverse engineering Signal processing algorithms Space exploration structural obfuscation System on chip Transformations
Title	DSP design protection in CE through algorithmic transformation based structural obfuscation
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