Fault Detection in Blowfish Algorithm Using FPGA-Based Modified Decision Tree Approach

This research article identifies the fault occurrence in the blowfish cryptography algorithm using a modified Decision Tree classifier. Though there are several cryptography algorithms, the symmetric blowfish algorithm is considered for its high performance, compatibility, security, and ease of impl...

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Bibliographic Details
Published in:IEEE access Vol. 13; pp. 90591 - 90600
Main Authors: Prathap, Joseph Anthony, Sathiyanarayanan, Mithileysh
Format: Journal Article
Language:English
Published: Piscataway IEEE 2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Blowfish cryptography algorithm
Ciphers
Circuit faults
Cryptography
decision tree algorithm
Decision trees
Encryption
Fault detection
Fault diagnosis
fault identification
field programmable gate array
Field programmable gate arrays
Hardware
Integrated circuits
Real time
Real-time systems
S Box
Security
System on chip
system-on-chip design
ISSN:2169-3536, 2169-3536
Online Access:Get full text
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Summary:This research article identifies the fault occurrence in the blowfish cryptography algorithm using a modified Decision Tree classifier. Though there are several cryptography algorithms, the symmetric blowfish algorithm is considered for its high performance, compatibility, security, and ease of implementation. When utilized in real applications, the attack in the bit transmission either at the encryption or at the decryption might affect its authentication and security. This demands automatic fault identification within the blowfish algorithm using a modified Decision tree. This work includes attack induction and identification of the same using the developed modified decision tree-based equality checker circuit. The proposed method involves the development of an equality-checker-based decision tree algorithm to form 12 sections for the 16 iterations from the encryption and decryption process of the blowfish algorithm. The FPGA device implements the proposed method to validate the real-time feasibility. Also, the System on Chip IC layout is developed for the proposed method to analyze the parameters of power and area using the EDA tools. The utilization of FPGA in indicating the attack of the blowfish algorithm is evaluated for its high-performance capability that has low latency and higher throughput for the 64-bit design resolution.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2025.3567659