Enhancing High-Level Synthesis Using a Meta-Programming Approach

In today's increasingly heterogeneous compute landscape, there is high demand for design tools that offer seemingly contradictory features: portable programming abstractions that hide underlying architectural detail, and the capability to optimise and exploit architectural features. Our meta-pr...

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Veröffentlicht in:IEEE transactions on computers Jg. 70; H. 12; S. 2043 - 2055
Hauptverfasser: Vandebon, Jessica, de Figueiredo Coutinho, Jose, Luk, Wayne, Nurvitadhi, Eriko
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.12.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:0018-9340, 1557-9956
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Abstract In today's increasingly heterogeneous compute landscape, there is high demand for design tools that offer seemingly contradictory features: portable programming abstractions that hide underlying architectural detail, and the capability to optimise and exploit architectural features. Our meta-programming approach, Artisan, decouples application functionality from optimisation concerns to address the complexity of mapping high-level application descriptions onto heterogeneous platforms from which they are abstracted. With Artisan, application experts focus on algorithmic behaviour, while platform and domain experts focus on optimisation and mapping. Artisan offers complete design-flow orchestration in a unified programming environment based on Python 3 to enable accessible codification of reusable optimisation strategies that can be automatically applied to high-level application descriptions. We have developed and evaluated an Artisan prototype and a set of customised meta-programs used to automatically optimise six case study applications for CPU+FPGA targets. In our experiments, Artisan-optimised designs achieve the same order of magnitude speedup as manually optimised designs compared to corresponding unoptimised software.
AbstractList In today's increasingly heterogeneous compute landscape, there is high demand for design tools that offer seemingly contradictory features: portable programming abstractions that hide underlying architectural detail, and the capability to optimise and exploit architectural features. Our meta-programming approach, Artisan, decouples application functionality from optimisation concerns to address the complexity of mapping high-level application descriptions onto heterogeneous platforms from which they are abstracted. With Artisan, application experts focus on algorithmic behaviour, while platform and domain experts focus on optimisation and mapping. Artisan offers complete design-flow orchestration in a unified programming environment based on Python 3 to enable accessible codification of reusable optimisation strategies that can be automatically applied to high-level application descriptions. We have developed and evaluated an Artisan prototype and a set of customised meta-programs used to automatically optimise six case study applications for CPU+FPGA targets. In our experiments, Artisan-optimised designs achieve the same order of magnitude speedup as manually optimised designs compared to corresponding unoptimised software.
Author Nurvitadhi, Eriko
de Figueiredo Coutinho, Jose
Luk, Wayne
Vandebon, Jessica
Author_xml – sequence: 1
  givenname: Jessica
  orcidid: 0000-0002-1327-9712
  surname: Vandebon
  fullname: Vandebon, Jessica
  email: jessica.vandebon17@imperial.ac.uk
  organization: Imperial College London, London, U.K
– sequence: 2
  givenname: Jose
  surname: de Figueiredo Coutinho
  fullname: de Figueiredo Coutinho, Jose
  email: Gabriel.Figueiredo@imperial.ac.uk
  organization: Imperial College London, London, U.K
– sequence: 3
  givenname: Wayne
  surname: Luk
  fullname: Luk, Wayne
  email: w.luk@imperial.ac.uk
  organization: Imperial College London, London, U.K
– sequence: 4
  givenname: Eriko
  surname: Nurvitadhi
  fullname: Nurvitadhi, Eriko
  email: eriko.nurvitadhi@intel.com
  organization: Intel Corporation, San Jose, CA, USA
BookMark eNp9kE1rAjEQhkOxULU999DLQs-rk6_d5FZZbC1YWqieQzZGN6JZm6wF_313UXrooTDDwMz7zDDvAPV87S1C9xhGGIMcL4oRAYJHFGTGiLxCfcx5nkrJsx7qA2CRSsrgBg1i3AJARkD20dPUV9ob5zfJzG2qdG6_7S75PPmmstHFZBm7kU7ebKPTj1Bvgt7vu9bkcAi1NtUtul7rXbR3lzpEy-fpopil8_eX12IyTw0Rskkxs8aUhlNLBbGc5iInxpAMr3hWrtas5ACGmzInWWY5aNG-JDUrBVu1wYAO0eN5b3v262hjo7b1Mfj2pCJc8hwLKlmr4meVCXWMwa6VcY1uXO2boN1OYVCdWWpRqM4sdTGr5cZ_uENwex1O_xAPZ8JZa3_VkgmatfkDxK90jw
CODEN ITCOB4
CitedBy_id crossref_primary_10_1109_TCSII_2024_3353690
crossref_primary_10_1145_3640464
Cites_doi 10.1109/CGO.2019.8661197
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10.1016/j.cl.2017.12.003
10.1145/2627373.2627387
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10.1145/2584665
10.1109/FCCM48280.2020.00032
10.1109/TC.2011.205
10.1145/3278122.3278131
ContentType Journal Article
Copyright Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021
Copyright_xml – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021
DBID 97E
RIA
RIE
AAYXX
CITATION
7SC
7SP
8FD
JQ2
L7M
L~C
L~D
DOI 10.1109/TC.2021.3096429
DatabaseName IEEE All-Society Periodicals Package (ASPP) 2005-present
IEEE All-Society Periodicals Package (ASPP) 1998-Present
IEEE Electronic Library (IEL)
CrossRef
Computer and Information Systems Abstracts
Electronics & Communications Abstracts
Technology Research Database
ProQuest Computer Science Collection
Advanced Technologies Database with Aerospace
Computer and Information Systems Abstracts – Academic
Computer and Information Systems Abstracts Professional
DatabaseTitle CrossRef
Technology Research Database
Computer and Information Systems Abstracts – Academic
Electronics & Communications Abstracts
ProQuest Computer Science Collection
Computer and Information Systems Abstracts
Advanced Technologies Database with Aerospace
Computer and Information Systems Abstracts Professional
DatabaseTitleList Technology Research Database

Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
Computer Science
EISSN 1557-9956
EndPage 2055
ExternalDocumentID 10_1109_TC_2021_3096429
9483648
Genre orig-research
GrantInformation_xml – fundername: SRC Artificial Intelligence Hardware Task
  grantid: 3020.001
– fundername: U.K. EPSRC
  grantid: EP/L016796/1; EP/N031768/1; EP/P010040/1; EP/S030069/1; EP/L00058X/1
– fundername: Intel
GroupedDBID --Z
-DZ
-~X
.DC
0R~
29I
4.4
5GY
6IK
85S
97E
AAJGR
AARMG
AASAJ
AAWTH
ABAZT
ABQJQ
ABVLG
ACGFO
ACIWK
ACNCT
AENEX
AETEA
AGQYO
AHBIQ
AKJIK
AKQYR
ALMA_UNASSIGNED_HOLDINGS
ASUFR
ATWAV
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CS3
DU5
EBS
EJD
HZ~
IEDLZ
IFIPE
IPLJI
JAVBF
LAI
M43
MS~
O9-
OCL
P2P
PQQKQ
RIA
RIE
RNS
RXW
TAE
TN5
TWZ
UHB
UPT
XZL
YZZ
.55
3EH
3O-
5VS
AAYXX
ABFSI
ABUFD
AETIX
AGSQL
AI.
AIBXA
ALLEH
CITATION
E.L
H~9
IAAWW
IBMZZ
ICLAB
IFJZH
MVM
RNI
RZB
UKR
VH1
X7M
XOL
YXB
YYQ
ZCG
7SC
7SP
8FD
JQ2
L7M
L~C
L~D
ID FETCH-LOGICAL-c289t-14eccbc53e382e537872cc261d56bdf4b500c5cb7266e50a81099a4b84d84d403
IEDL.DBID RIE
ISICitedReferencesCount 6
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000716693400004&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN 0018-9340
IngestDate Sun Nov 30 05:34:13 EST 2025
Sat Nov 29 01:35:42 EST 2025
Tue Nov 18 20:48:54 EST 2025
Wed Aug 27 05:08:51 EDT 2025
IsPeerReviewed true
IsScholarly true
Issue 12
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-c289t-14eccbc53e382e537872cc261d56bdf4b500c5cb7266e50a81099a4b84d84d403
Notes ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ORCID 0000-0002-1327-9712
PQID 2595718394
PQPubID 85452
PageCount 13
ParticipantIDs ieee_primary_9483648
proquest_journals_2595718394
crossref_primary_10_1109_TC_2021_3096429
crossref_citationtrail_10_1109_TC_2021_3096429
PublicationCentury 2000
PublicationDate 2021-12-01
PublicationDateYYYYMMDD 2021-12-01
PublicationDate_xml – month: 12
  year: 2021
  text: 2021-12-01
  day: 01
PublicationDecade 2020
PublicationPlace New York
PublicationPlace_xml – name: New York
PublicationTitle IEEE transactions on computers
PublicationTitleAbbrev TC
PublicationYear 2021
Publisher IEEE
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher_xml – name: IEEE
– name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
References ref13
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References_xml – year: 2020
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– ident: ref1
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SSID ssj0006209
Score 2.3808076
Snippet In today's increasingly heterogeneous compute landscape, there is high demand for design tools that offer seemingly contradictory features: portable...
SourceID proquest
crossref
ieee
SourceType Aggregation Database
Enrichment Source
Index Database
Publisher
StartPage 2043
SubjectTerms Codification
Descriptions
Field programmable gate arrays
FPGA
Heterogeneous computing
Heterogeneous networks
High level synthesis
Mapping
meta-programming
Optimization
Programming
Programming environments
Programming languages
Python
Task analysis
Title Enhancing High-Level Synthesis Using a Meta-Programming Approach
URI https://ieeexplore.ieee.org/document/9483648
https://www.proquest.com/docview/2595718394
Volume 70
WOSCitedRecordID wos000716693400004&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
journalDatabaseRights – providerCode: PRVIEE
  databaseName: IEEE Xplore
  customDbUrl:
  eissn: 1557-9956
  dateEnd: 99991231
  omitProxy: false
  ssIdentifier: ssj0006209
  issn: 0018-9340
  databaseCode: RIE
  dateStart: 19680101
  isFulltext: true
  titleUrlDefault: https://ieeexplore.ieee.org/
  providerName: IEEE
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwFH5sw4MenG6K0yk9ePBgt7RJm_TmGA4PcwycsFtJ0kwH2sl-CP73JmlWBfUg9FBK0pa8vrzvNV--B3ApTJ0QDVx9iij3iQi0zyUy9jkPdbhlMhGZlcwf0tGITafJuALX5V4YpZQln6mOObVr-dlCbsyvsm5CGI4Jq0KVUlrs1Spn3XhL59DPTTBBTsYnQEl30td5YBh0sIbrxGLJrwhkS6r8mIdtcBnU__daB7DvQKTXK6x-CBWVN6C-LdDgOX9twN43tcEm3Nzmz0ZdI3_yDLvDHxq-kPfwkWsMuJqvPMse8Lh3r9bcHxe8rVdzqed0x4_gcXA76d_5roCCL3UetfYDog0kZIQVZqGKsHbOUEqdM2VRLLIZERFCMpKC6iitIsSZWSbjRDCS6YMgfAy1fJGrE_AwYlxgLApFuQAzReOAx5TPUDSbYd6CznZQU-nUxU2Ri5fUZhkoSSf91FghdVZowVXZ4a0Q1vi7adMMetnMjXcL2lurpc7xVqnO5iJqUB85_b3XGeyaexeMlDbU1suNOocd-b6er5YX9pv6BFShxrM
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwFH7MKagHf4vzZw8ePNgtbZI2vSljoriNgRN2K0ma6UA7sVPwvzdJ0ymoB6GHUhJS8vryvtd8-R7AqTB1QjRw9WMUc5-IQPtcIiOf81CHWyYTkVnJ_G7c77PRKBnU4Hx-FkYpZclnqmlu7V5-NpVv5ldZKyEMR4QtwCIlJAzK01rzdTeqCB165AQT5IR8ApS0hm2dCYZBE2vATiya_IpBtqjKj5XYhper9f-92AasORjpXZZ234SayrdgvSrR4DmP3YLVb3qD23DRyR-Nvkb-4Bl-h981jCHv7iPXKLCYFJ7lD3jc66kZ9wclc-vZPLp0yuM7cH_VGbavfVdCwZc6k5r5AdEmEpJihVmoKNbuGUqps6aMRiIbE0ERklSKWMdpRRFnZqOME8FIpi-C8C7U82mu9sDDiHGBsSg15QLMVBwFPIr5GNHxGPMGNKtJTaXTFzdlLp5Sm2egJB22U2OF1FmhAWfzDi-ltMbfTbfNpM-bufluwGFltdS5XpHqfI7GBveR_d97ncDy9bDXTbs3_dsDWDHjlPyUQ6jPXt_UESzJ99mkeD2239cn12vJ-g
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Enhancing+High-Level+Synthesis+Using+a+Meta-Programming+Approach&rft.jtitle=IEEE+transactions+on+computers&rft.au=Vandebon%2C+Jessica&rft.au=de+Figueiredo+Coutinho%2C+Jose&rft.au=Luk%2C+Wayne&rft.au=Nurvitadhi%2C+Eriko&rft.date=2021-12-01&rft.pub=The+Institute+of+Electrical+and+Electronics+Engineers%2C+Inc.+%28IEEE%29&rft.issn=0018-9340&rft.eissn=1557-9956&rft.volume=70&rft.issue=12&rft.spage=2043&rft_id=info:doi/10.1109%2FTC.2021.3096429&rft.externalDBID=NO_FULL_TEXT
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0018-9340&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0018-9340&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0018-9340&client=summon