Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits

The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS bina...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers Vol. C-35; no. 2; pp. 157 - 161
Main Authors: MANGIN, J. L, CURRENT, K. W
Format: Journal Article
Language:English
Published: New York, NY IEEE 01.02.1986
Institute of Electrical and Electronics Engineers
Subjects:
Applied sciences
Circuits
Coding, codes
Decoding
Delays
Detectors
Exact sciences and technology
Four-valued signaling
Information, signal and communications theory
Inverters
Logic
Logic gates
Propagation delay
quaternary logic encoders and decoders
Semiconductor device measurement
Signal and communications theory
Telecommunications and information theory
VLSI chip interfaces
Logic circuit
Decoding circuit
VLSI circuit
Complementary MOS technology
Coding circuit
Interface
ISSN:0018-9340, 1557-9956
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS binary-to-quaternary encoder and quaternary-to-binary decoder test circuits that have been realized on a gate array IC chip.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.1986.1676733