High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-di...

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Veröffentlicht in:	IEEE transactions on computers Jg. C-34; H. 9; S. 789 - 796
Hauptverfasser:	TAKAGI, N, YASUURA, H, YAJIMA, S
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York, NY IEEE 01.09.1985 Institute of Electrical and Electronics Engineers
Schlagworte:	Adders Algorithmics. Computability. Computer arithmetics Applied sciences Arithmetic operations binary integer multiplication Binary trees carry-propagation-free adder Combinational circuits Computer science; control theory; systems Computers Exact sciences and technology Hardware hardware algorithm high-speed multiplier Layout Logic gates redundant binary representation Signal processing algorithms signed-digit number representation Theoretical computing Very large scale integration VLSI Wires Computers arithmetic Multiplication VLSI circuit Binary tree Redundancy Multiplier Algorithm
ISSN:	0018-9340, 1557-9956
Online-Zugang:	Volltext
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