High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-di...

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Vydáno v:IEEE transactions on computers Ročník C-34; číslo 9; s. 789 - 796
Hlavní autoři: TAKAGI, N, YASUURA, H, YAJIMA, S
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York, NY IEEE 01.09.1985
Institute of Electrical and Electronics Engineers
Témata:
Adders
Algorithmics. Computability. Computer arithmetics
Applied sciences
Arithmetic operations
binary integer multiplication
Binary trees
carry-propagation-free adder
Combinational circuits
Computer science; control theory; systems
Computers
Exact sciences and technology
Hardware
hardware algorithm
high-speed multiplier
Layout
Logic gates
redundant binary representation
Signal processing algorithms
signed-digit number representation
Theoretical computing
Very large scale integration
VLSI
Wires
Computers arithmetic
Multiplication
VLSI circuit
Binary tree
Redundancy
Multiplier
Algorithm
ISSN:0018-9340, 1557-9956
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Popis
Shrnutí:A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.1985.1676634