Coupling of a lightweight model of reduced convolutional autoencoder with linear SVM classifier to detect brain tumours on FPGA

In the field of computer assisted diagnosis, classification of tumours using lightweight machine learning algorithms require a complete detection chain of pattern recognition process. The diagnosis system can be made portable by using Field Programmable Gate Arrays (FPGAs) which accommodates the cap...

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Vydané v:Expert systems with applications Ročník 290; s. 128444
Hlavní autori: Chatterjee, Soumita, Pandit, Soumya, Das, Arpita
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Elsevier Ltd 25.09.2025
Predmet:
Brain Tumour
Feature maps
FPGAs
Linear SVM
Loop unrolling
Reduced Convolutional Autoencoder
FPGAs
Feature maps
Reduced Convolutional Autoencoder
Linear SVM
Brain Tumour
Loop unrolling
ISSN:0957-4174
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Popis
Shrnutí:In the field of computer assisted diagnosis, classification of tumours using lightweight machine learning algorithms require a complete detection chain of pattern recognition process. The diagnosis system can be made portable by using Field Programmable Gate Arrays (FPGAs) which accommodates the capabilities of high speed parallel processing. This work proposes the design of a lightweight custom Intellectual Property (IP) core on FPGA to discriminate brain tumours into benign and malignant categories. The framework of the proposed IP core is initiated by a preprocessing module to get a clear outline of tumours. Following this preprocessing step, a dual-stack Reduced Convolutional Autoencoder (RCA) unit is coupled with a linear Support Vector Machine (SVM) classifier. The proposed RCA unit extracts a set of 64 numbers of significant feature maps which in turn eliminate the necessity of deep learning based complex classifiers. This IP core has been tested and validated by the standard benchmark datasets of brain tumours and we have found the overall accuracy of 98.77 % using only 3.08 % of available resources in the FPGA board. Further, inclusion of loop unrolling optimization technique boosts up its pipeline processing power. In this view, the customized design of such lightweight embedded IP core is able to resolve the challenges of achieving high quality results in a resource/power constrained environment.
ISSN:0957-4174
DOI:10.1016/j.eswa.2025.128444