Real Time FPGA Implementation of a High Speed for Video Encryption and Decryption System with High Level Synthesis Tools

The development of communication networks has made information security more important than ever for both transmission and storage. Since the majority of networks involve images, image security is becoming a difficult challenge. In order to provide real-time image encryption and decryption, this stu...

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Vydáno v:International journal of advanced computer science & applications Ročník 15; číslo 1
Hlavní autor: Alhomoud, Ahmed
Médium: Journal Article
Jazyk:angličtina
Vydáno: West Yorkshire Science and Information (SAI) Organization Limited 2024
Témata:
Algorithms
Coders
Communication networks
Computer science
Data encryption
Design techniques
Embedded systems
Encryption
Field programmable gate arrays
Hardware
High level synthesis
Information technology
Internet of Things
Matlab
Network security
Real time
Security
Security systems
Software
Video data
Vision systems
ISSN:2158-107X, 2156-5570
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Shrnutí:The development of communication networks has made information security more important than ever for both transmission and storage. Since the majority of networks involve images, image security is becoming a difficult challenge. In order to provide real-time image encryption and decryption, this study suggests an FPGA implementation of a video cryptosystem that has been well-optimized based on high level synthesis. The MATLAB HDL coder and Vivado Tools from Xilinx are used in the design, implementation, and validation of the algorithm on the Xilinx Zynq FPGA platform. Low resource consumption and pipeline processing are well-suited to the hardware architecture. For real-time applications involving secret picture encryption and decryption, the suggested hardware approach is widely utilized. This study suggests an implementation of the encryption-decryption system that is both very efficient and area-optimized. A unique high-level synthesis (HLS) design technique based on application-specific bit widths for intermediate data nodes was used to realize the proposed implementation. For HLS, MATLAB HDL coder was used to generate register transfer level RTL design. Using Vivado software, the RTL design was implemented on the Xilinx ZedBoard, and its functioning was tested in real time using an input video stream. The results produced are faster and more area- efficient (target FPGA has fewer gates than before) than those of earlier solutions for the same target board.
Bibliografie:ObjectType-Article-1
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ISSN:2158-107X
2156-5570
DOI:10.14569/IJACSA.2024.0150172