Multiple Leads With a Switch Mode for Lossless and Lossy Compression Using Very-Large-Scale Integration Technology

Electrocardiogram monitoring is crucial for the prevention and treatment of cardiovascular diseases. In this paper, we developed a wearable device involving multiple leads that monitors cardiac electrical activity using very large-scale integration technology to facilitate long-term activity monitor...

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Vydáno v:IEEE access Ročník 6; s. 67291 - 67300
Hlavní autoři: Tseng, Yun-Hua, Chen, Yuan-Ho, Lu, Chih-Wen
Médium: Journal Article
Jazyk:angličtina
Vydáno: Piscataway IEEE 2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Biomedical monitoring
bit compression ratio
Chest
Circuits
CMOS
Compression algorithms
Compression ratio
Electrocardiogram (ECG)
Electrocardiography
Gate counting
Hardware
lossless compression algorithm
lossy compression algorithm
Monitoring
multiple leads
Power consumption
Power demand
Switches
Technology utilization
Very large scale integration
Wearable technology
ISSN:2169-3536, 2169-3536
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Shrnutí:Electrocardiogram monitoring is crucial for the prevention and treatment of cardiovascular diseases. In this paper, we developed a wearable device involving multiple leads that monitors cardiac electrical activity using very large-scale integration technology to facilitate long-term activity monitoring. In addition to using limb leads and augmented limb leads for monitoring heart activity, six unipolar chest leads were attached to six positive electrodes and placed on the surface of the chest to record electrical activity of different regions of the heart. The multiple leads lie perpendicular to the frontal plane and were integrated within a single circuit to reduce hardware costs and size of the device. The proposed architecture also allows users to switch between lossless and lossy compression to control the power consumption and bit compression ratio. The effectiveness of the proposed approach was verified by fabricating a chip using 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology. The proposed architecture core has an operating frequency of 41 MHz and a gate count of 4K.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2018.2879412