Hierarchical all-zero block early determination algorithm for low-complexity versatile video coding

Driven by the rapid advancement of communication technologies, there is a growing demand for real-time ultra-high-definition video transmission. Versatile Video Coding (VVC), the state-of-the-art video compression standard, achieves comparable visual quality at approximately 50% lower bit rate than...

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Bibliographic Details
Published in:Journal of real-time image processing Vol. 22; no. 6; p. 215
Main Authors: Li, Shangqia, Lai, Changcai, Huang, Xiaofeng, Cui, Yan, Yu, Dingguo, Zhou, Yang, Yin, Haibing
Format: Journal Article
Language:English
Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.12.2025
Springer Nature B.V
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ISSN:1861-8200, 1861-8219
Online Access:Get full text
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Summary:Driven by the rapid advancement of communication technologies, there is a growing demand for real-time ultra-high-definition video transmission. Versatile Video Coding (VVC), the state-of-the-art video compression standard, achieves comparable visual quality at approximately 50% lower bit rate than its predecessor, High Efficiency Video Coding (HEVC). However, the adoption of advanced coding tools in VVC, such as dependent quantization (DQ) and affine motion prediction, results in a multi-fold increase in computational complexity compared to HEVC, which impedes its real-time related applications. To mitigate computational complexity while preserving coding efficiency, this paper introduces a hierarchical all-zero block (AZB) early determination algorithm for low-complexity VVC, encompassing genuine AZB verification, pseudo-AZB identification, and early all-zero coefficient group (CG) termination. Firstly, to skip transform unit (TU) level zero blocks, a genuine all-zero block (GAZB) detection method is proposed by analyzing scalar quantization, where an empirical threshold is derived to identify the position of the last significant coefficient. Then, to further skip the TU level zero blocks, a pseudo all-zero block (PAZB) skip method is proposed by implementing a rate estimation model to estimate the bit rate before the DQ process. Finally, a novel rate-distortion (RD) cost prediction model is proposed to skip CG-level zero blocks. The proposed method is implemented on the VVC test model 10.0 (VTM - 10.0), and the experimental results show that the proposed method achieves 5.87% time saving with only 0.75% BD-rate increase.
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ISSN:1861-8200
1861-8219
DOI:10.1007/s11554-025-01787-8