Cyclic memory: a low-latency, single-buffer technique for FMCW LiDAR interleaving/de-interleaving

Pipelined systems have long proven their efficiency in high-throughput data processing by enabling concurrent execution of sequential tasks. However, a recurring challenge in such systems is the mismatch between order of data generation and consumption across pipeline stages. This problem imposes a...

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Vydáno v:	Analog integrated circuits and signal processing Ročník 124; číslo 3; s. 70
Hlavní autoři:	Hafez, O. S., Abouelfetouh, O. A., Mohamed, Y. O., Hasaneen, M. N., Fathy, O. H., Hassan, Y. H., Mahroos, M. M., Elomda, R. A., Ghouneem, M. M.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York Springer US 01.09.2025 Springer Nature B.V
Témata:	Algorithms Buffers Circuits and Systems Code Division Multiple Access Data acquisition Data processing Electrical Engineering Engineering Fourier transforms Lidar Reading Signal,Image and Speech Processing Table tennis Writing DSP FMCW FPGA Memories LiDAR Group theory
ISSN:	0925-1030, 1573-1979
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Abstract	Pipelined systems have long proven their efficiency in high-throughput data processing by enabling concurrent execution of sequential tasks. However, a recurring challenge in such systems is the mismatch between order of data generation and consumption across pipeline stages. This problem imposes a critical constraint: the system must collect new data block while simultaneously reorganizing previously acquired data block–all without interrupting pipeline throughput. A ping-pong buffer allows a system to do so by doubling buffering memory size. This idea increases memory data throughput by not halting the pipeline operation. This paper presents a memory read/write algorithm called “Cyclic Memory” as an alternative to the ping-pong buffering algorithm for the data interleaving/de-interleaving process. Unlike the ping-pong buffering algorithm, the cyclic memory algorithm does not require double buffering. This means that cyclic memory cuts memory requirements in half, uses less area, and consumes less power. This paper will discuss the derivation of the algorithm as well as its implementation.
AbstractList	Pipelined systems have long proven their efficiency in high-throughput data processing by enabling concurrent execution of sequential tasks. However, a recurring challenge in such systems is the mismatch between order of data generation and consumption across pipeline stages. This problem imposes a critical constraint: the system must collect new data block while simultaneously reorganizing previously acquired data block–all without interrupting pipeline throughput. A ping-pong buffer allows a system to do so by doubling buffering memory size. This idea increases memory data throughput by not halting the pipeline operation. This paper presents a memory read/write algorithm called “Cyclic Memory” as an alternative to the ping-pong buffering algorithm for the data interleaving/de-interleaving process. Unlike the ping-pong buffering algorithm, the cyclic memory algorithm does not require double buffering. This means that cyclic memory cuts memory requirements in half, uses less area, and consumes less power. This paper will discuss the derivation of the algorithm as well as its implementation.
ArticleNumber	70
Author	Abouelfetouh, O. A. Fathy, O. H. Ghouneem, M. M. Hafez, O. S. Hassan, Y. H. Mohamed, Y. O. Hasaneen, M. N. Mahroos, M. M. Elomda, R. A.
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Cites_doi	10.1109/TCE.2008.4560094 10.1109/CDCIEM.2012.187 10.5755/j01.eee.21.2.7606 10.1117/12.476412 10.1117/12.486977 10.1109/MSP.2019.2909074 10.1109/ICM63406.2024.10815748
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SubjectTerms	Algorithms Buffers Circuits and Systems Code Division Multiple Access Data acquisition Data processing Electrical Engineering Engineering Fourier transforms Lidar Reading Signal,Image and Speech Processing Table tennis Writing
Title	Cyclic memory: a low-latency, single-buffer technique for FMCW LiDAR interleaving/de-interleaving
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