APA (7th ed.) Citation

Haridas, S. G., & Ziavras, S. G. (2004). FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. Parallel algorithms and applications, 19(4), 211-226. https://doi.org/10.1080/10637190412331279957

Chicago Style (17th ed.) Citation

Haridas, Satchidanand G., and Sotirios G. Ziavras. "FPGA Implementation of a Cholesky Algorithm for a Shared-memory Multiprocessor Architecture." Parallel Algorithms and Applications 19, no. 4 (2004): 211-226. https://doi.org/10.1080/10637190412331279957.

MLA (9th ed.) Citation

Haridas, Satchidanand G., and Sotirios G. Ziavras. "FPGA Implementation of a Cholesky Algorithm for a Shared-memory Multiprocessor Architecture." Parallel Algorithms and Applications, vol. 19, no. 4, 2004, pp. 211-226, https://doi.org/10.1080/10637190412331279957.