Theoretical insights into the impact of border and interface traps on hysteresis in monolayer MoS2 FETs

Threshold voltage hysteresis ΔVh in two-dimensional transistor transfer characteristics poses a bottleneck in achieving stable 2D CMOS integrated circuits. Hysteresis is primarily attributed to traps at the channel/oxide interface as well as in the oxide. In this study, we present a physics-based se...

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Veröffentlicht in:	Microelectronic engineering Jg. 299; S. 112333
Hauptverfasser:	Ghosh, Rittik, Provias, Alexandros, Karl, Alexander, Wilhelmer, Christoph, Knobloch, Theresia, Davoudi, Mohammad Rasool, Sattari-Esfahlan, Seyed Mehdi, Waldhör, Dominic, Grasser, Tibor
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Elsevier B.V 15.09.2025
Schlagworte:	2D FET CMOS Hysteresis Physics-based models Reliability CMOS Physics-based models Reliability Hysteresis 2D FET
ISSN:	0167-9317
Online-Zugang:	Volltext
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