Theoretical insights into the impact of border and interface traps on hysteresis in monolayer MoS2 FETs

Threshold voltage hysteresis ΔVh in two-dimensional transistor transfer characteristics poses a bottleneck in achieving stable 2D CMOS integrated circuits. Hysteresis is primarily attributed to traps at the channel/oxide interface as well as in the oxide. In this study, we present a physics-based se...

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Bibliographic Details
Published in:Microelectronic engineering Vol. 299; p. 112333
Main Authors: Ghosh, Rittik, Provias, Alexandros, Karl, Alexander, Wilhelmer, Christoph, Knobloch, Theresia, Davoudi, Mohammad Rasool, Sattari-Esfahlan, Seyed Mehdi, Waldhör, Dominic, Grasser, Tibor
Format: Journal Article
Language:English
Published: Elsevier B.V 15.09.2025
Subjects:
2D FET
CMOS
Hysteresis
Physics-based models
Reliability
CMOS
Physics-based models
Reliability
Hysteresis
2D FET
ISSN:0167-9317
Online Access:Get full text
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Summary:Threshold voltage hysteresis ΔVh in two-dimensional transistor transfer characteristics poses a bottleneck in achieving stable 2D CMOS integrated circuits. Hysteresis is primarily attributed to traps at the channel/oxide interface as well as in the oxide. In this study, we present a physics-based self-consistent modeling framework to investigate the impact of border and interface traps on ΔVh and apply it to monolayer (1-L) MoS2 field-effect transistors (FETs). The transient trapping and detrapping of charges during gate voltage sweeps across a wide range of frequencies and temperatures is analyzed using a two-state non-radiative multi-phonon (NMP) model. Our results reveal distinct dynamic responses for slow border and fast interface traps, with border traps exhibiting slower time constants due to larger relaxation energies and interface traps showing fast nuclear tunneling-dominated dynamics resulting from the smaller relaxation energies. These simulations highlights the critical role of the spatial and energetic distributions of the traps in determining ΔVh, providing insights into the stability of 2D FETs and paving the way for improved device engineering.
ISSN:0167-9317
DOI:10.1016/j.mee.2025.112333