Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the...

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Vydané v:	International journal of parallel programming Ročník 52; číslo 5-6; s. 367 - 379
Hlavný autor:	Sanlı, Mustafa
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York Springer US 01.12.2024 Springer Nature B.V
Predmet:	Algorithms Computer architecture Computer Science Cryptography Data processing Field programmable gate arrays Hardware High performance systems Information systems Parallel processing Performance evaluation Pipelining (computers) Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation Hash function FPGA Embedded system Keccak
ISSN:	0885-7458, 1573-7640
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