Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the...

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Veröffentlicht in:	International journal of parallel programming Jg. 52; H. 5-6; S. 367 - 379
1. Verfasser:	Sanlı, Mustafa
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York Springer US 01.12.2024 Springer Nature B.V
Schlagworte:	Algorithms Computer architecture Computer Science Cryptography Data processing Field programmable gate arrays Hardware High performance systems Information systems Parallel processing Performance evaluation Pipelining (computers) Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation Hash function FPGA Embedded system Keccak
ISSN:	0885-7458, 1573-7640
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Abstract	The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the Keccak algorithm to address this problem. Our proposed hardware architecture exploits existing parallelisms in the Keccak algorithm to optimize its execution in terms of both speed and resource efficiency. By thoroughly analyzing the Keccak algorithm's structure and building blocks, we adapted our hardware architecture to take full advantage of the capabilities of modern FPGAs and ASICs. Key features of the high-performance hardware architecture include parallelized computation blocks, efficient digital design and a streamlined data path. In addition to these, we also make use of hardware level design considerations such as FPGA floorplanning, pipelining and bit-level parallelisms to increase the performance of our design. All these design considerations contribute to significantly increased processing speeds surpassing traditional software-based approaches and previous hardware-based implementations. Our design also minimizes resource usage, making it applicable to a wide variety of embedded and cryptographic systems. This makes our design suitable for applications that require both high throughput and secure data processing.
AbstractList	The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the Keccak algorithm to address this problem. Our proposed hardware architecture exploits existing parallelisms in the Keccak algorithm to optimize its execution in terms of both speed and resource efficiency. By thoroughly analyzing the Keccak algorithm's structure and building blocks, we adapted our hardware architecture to take full advantage of the capabilities of modern FPGAs and ASICs. Key features of the high-performance hardware architecture include parallelized computation blocks, efficient digital design and a streamlined data path. In addition to these, we also make use of hardware level design considerations such as FPGA floorplanning, pipelining and bit-level parallelisms to increase the performance of our design. All these design considerations contribute to significantly increased processing speeds surpassing traditional software-based approaches and previous hardware-based implementations. Our design also minimizes resource usage, making it applicable to a wide variety of embedded and cryptographic systems. This makes our design suitable for applications that require both high throughput and secure data processing.
Author	Sanlı, Mustafa
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Cites_doi	10.3390/computation7040063 10.1142/S0218126616500262 10.1109/TCAD.2014.2307002 10.3390/mi14061129 10.1109/COMST.2021.3126127 10.1109/ISQED.2017.7918336 10.1109/ISVLSI.2017.24 10.51758/AGJSR-01-2012-0003 10.1109/ACOMP53746.2021.00029 10.1109/ICM50269.2020.9331803 10.1109/MECO.2015.7181868 10.1109/DSD.2012.63 10.1142/S0218126616500699 10.1109/SysCoBIoTS48768.2019.9028028
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SubjectTerms	Algorithms Computer architecture Computer Science Cryptography Data processing Field programmable gate arrays Hardware High performance systems Information systems Parallel processing Performance evaluation Pipelining (computers) Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation
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Title	Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor
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