Analysis of Degradation Mechanisms of Gate Dielectrics Based on SiO2 in MOS Transistors

The current mathematical models of gate dielectric degradation are used to determine the value of a device’s operating time to failure depending on its internal properties and operating conditions. These models significantly reduce the time and material costs for testing and processing large amounts...

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Vydáno v:	Semiconductors (Woodbury, N.Y.) Ročník 55; číslo 13; s. 1045 - 1048
Hlavní autoři:	Eliseeva, D. A., Safonov, S. O.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Moscow Pleiades Publishing 01.12.2021 Springer Nature B.V
Témata:	Degradation Dielectrics Electric fields Elements of Integrated Electronics Magnetic Materials Magnetism Mathematical models MOS devices Physics Physics and Astronomy Semiconductor devices Silicon dioxide Thickness Transistors time-dependent dielectric breakdown MOS transistor gate dielectric reliability
ISSN:	1063-7826, 1090-6479
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Abstract	The current mathematical models of gate dielectric degradation are used to determine the value of a device’s operating time to failure depending on its internal properties and operating conditions. These models significantly reduce the time and material costs for testing and processing large amounts of experimental data. Here, the gate dielectrics based on SiO 2 in n - and p -channel MOS transistors are investigated. It is found that, when exposed to an electric field, the gate dielectric with the thickness of 5.3 nm most likely degrades according to the thermochemical model ( E -model), and the one with a thickness of 7 nm, according to the anode hole injection model (1/ E -model). The coefficients are calculated, and the analysis of mathematical models is carried out, which makes it possible to determine the lifetime of gate dielectrics based on SiO 2 7 nm thick in n - and p -channel MOS transistors and those that are 5.3 nm thick in n -channel MOS transistors at different values of their area, operating voltage, and temperature. This study can serve as a method for monitoring and determining the quality of the gate dielectrics of the manufactured MOS transistors.
AbstractList	The current mathematical models of gate dielectric degradation are used to determine the value of a device’s operating time to failure depending on its internal properties and operating conditions. These models significantly reduce the time and material costs for testing and processing large amounts of experimental data. Here, the gate dielectrics based on SiO2 in n- and p-channel MOS transistors are investigated. It is found that, when exposed to an electric field, the gate dielectric with the thickness of 5.3 nm most likely degrades according to the thermochemical model (E-model), and the one with a thickness of 7 nm, according to the anode hole injection model (1/E-model). The coefficients are calculated, and the analysis of mathematical models is carried out, which makes it possible to determine the lifetime of gate dielectrics based on SiO2 7 nm thick in n- and p-channel MOS transistors and those that are 5.3 nm thick in n-channel MOS transistors at different values of their area, operating voltage, and temperature. This study can serve as a method for monitoring and determining the quality of the gate dielectrics of the manufactured MOS transistors. The current mathematical models of gate dielectric degradation are used to determine the value of a device’s operating time to failure depending on its internal properties and operating conditions. These models significantly reduce the time and material costs for testing and processing large amounts of experimental data. Here, the gate dielectrics based on SiO 2 in n - and p -channel MOS transistors are investigated. It is found that, when exposed to an electric field, the gate dielectric with the thickness of 5.3 nm most likely degrades according to the thermochemical model ( E -model), and the one with a thickness of 7 nm, according to the anode hole injection model (1/ E -model). The coefficients are calculated, and the analysis of mathematical models is carried out, which makes it possible to determine the lifetime of gate dielectrics based on SiO 2 7 nm thick in n - and p -channel MOS transistors and those that are 5.3 nm thick in n -channel MOS transistors at different values of their area, operating voltage, and temperature. This study can serve as a method for monitoring and determining the quality of the gate dielectrics of the manufactured MOS transistors.
Author	Eliseeva, D. A. Safonov, S. O.
Author_xml	– sequence: 1 givenname: D. A. surname: Eliseeva fullname: Eliseeva, D. A. email: xoma2525@mail.ru organization: National Research University (MIET), OOO NM-Tech – sequence: 2 givenname: S. O. surname: Safonov fullname: Safonov, S. O. organization: OOO NM-Tech
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Cites_doi	10.1109/16.477595 10.1063/1.123228 10.1016/S0038-1101(02)00151-X 10.1109/IEDM.2012.6479123 10.1063/1.1565180 10.1007/978-3-319-43220-5
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Copyright	Pleiades Publishing, Ltd. 2021. ISSN 1063-7826, Semiconductors, 2021, Vol. 55, No. 13, pp. 1045–1048. © Pleiades Publishing, Ltd., 2021. ISSN 1063-7826, Semiconductors, 2021. © Pleiades Publishing, Ltd., 2021. Russian Text © The Author(s), 2020, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Elektronika, 2020, Vol. 25, No. 6, pp. 517–524.
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SubjectTerms	Degradation Dielectrics Electric fields Elements of Integrated Electronics Magnetic Materials Magnetism Mathematical models MOS devices Physics Physics and Astronomy Semiconductor devices Silicon dioxide Thickness Transistors
Title	Analysis of Degradation Mechanisms of Gate Dielectrics Based on SiO2 in MOS Transistors
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