Modified stable Euler-number algorithm implementation for real-time image binarization
The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In th...
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| Veröffentlicht in: | Journal of real-time image processing Jg. 9; H. 1; S. 31 - 45 |
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| Sprache: | Englisch |
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01.03.2014
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| ISSN: | 1861-8200, 1861-8219 |
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| Abstract | The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources. |
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| AbstractList | The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources. |
| Author | Amer, Aishy Abbasi, Naeem Athow, Jacques |
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| Keywords | Stable Euler Number Pipelined architecture FPGA Image binarization Real-time |
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| References | Berry, F., Chalimbaud, P.: Embedded active vision system based on FPGA architecture. EURASIP J.Embed. Syst. 12 (2007) Kundu, M.K., Murthy, C.A., Acharya, T., Bishnu, A., Bhattacharya, B.B.: On-chip computation of euler number of a binary image for efficient database search. In: Proceedings of the International Conference on Image Processing (ICIP), pp. 310–313 (2001) IacovielloD.IacovielloF.SantisA.D.BartolomeoO.D.Optimal binarization of images by neural networks for morphological analysis of ductile cast ironPattern Anal Appl20071012513310.1007/s10044-006-0052-8 CopeB.CheungP.LukW.HowesL.Performance comparison of graphics processors to reconfigurable logic: a case study Comput IEEE Transact201059443344810.1109/TC.2009.1792751812 HOL.: Higher order logic theorem prover. http://hol.sourceforge.net/ Jun 2012 Paul, L.R.: Thresholding for change detection. In: Sixth IEEE International Conference on Computer Vision, pp. 274–279 (1998) PikazA.AverbuchA.Digital image thresholding based on topological stable statePattern Recognit19962982984310.1016/0031-3203(95)00126-3 SnidaroL.ForestiG.L.“Real-time thresholding with euler numbers”Pattern Recognition Letters2003241533154410.1016/S0167-8655(02)00392-61048.68122 Ratnayake, K.; Amer, A.: An FPGA-based implementation of spatio-temporal object segmentation. In: Proceedings of the IEEE International Conference on Image Processing (ICIP), pp. 3265–3268 (2006) GrayS.B.Local properties of binary images in two dimensionsIEEE Transact Comput19712055156110.1109/T-C.1971.2232890216.50101 O’Gorman, L.: Binarization and multi-thresholding of document imnages using connectivity. In: Symposium on Document Analysis and Information Retrieval, pp. 237–252 (1994) Rosin, P., Ellis, T.: Image difference threshold strategies and shadow detection. In: British Machine Vision Conference, pp. 347–356 (1995) Sutter, G., Dechamps, J.P., Bioul, G.: Synthesis of arithmetic circuits. Wiley Interscience Edition, Blackwell, London (2006) Ashari, R.I., Hornsey, E.: FPGA implementation of real-time adaptive image thresholding. In: Proceedings of the SPIE, vol. 5578, pp. 410–419 (2004) Li, W., Huading, J., Binjie, L.: A new binarization algorithm based on maximum gradient of histogram. In: Fourth International Conference on Image and Graphics (ICIG), pp. 368–371 (2007) Owall, V., Hedberg, H., Kristensen, F.: Implementation of a labeling algorithm based on contour tracing with feature extraction. In: IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp. 1101–1104 (2007) Al-KofahiO.RoysamB.RadkeR.J.AndraS.Image change detection algorithms: a systematic surveyIEEE Transact Image Process20051429430710.1109/TIP.2004.8386982120664 Abbasi, N., Athow, J., Amer, A.: Effect of mask size on the cost/performance of spatial property calculator. Appendix A in: A real-time FPGA architecture of a modified stable Euler-number algorithm for Image binarization, Department of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Canada, Technical Report vidpro-TR-01-12,http://users.encs.concordia.ca/amer/paper/report/SENA.pdf (2012) Hesselbarth, S., Schunemann, T., Pirsch, P., Flatt, H., Blume, S.: A parallel hardware architecture for connected component labeling based on fast label merging. In: International Conference on Application-Specific systems, Architectures and Processors (ASAP 2008), pp. 144–149 (2008) Parhi, K.K.: VLSI digital signal processing systems, design and implementation. Blackwell, London (1999) Okuma, S., Yano, Y., Hashimiyama, T.: On-line filter generation for binary image processing using FPGA. In: Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics (SMC 99), vol. 5, pp. 565–570 (1999) KunduM.K.BishnuA.AcharyaT.DeyS.BhattacharyaB.B.A co-processor for computing the euler number of a binary image using divide-and-conquer strategyFundamenta Informaticae20077675891111.681412293051 Amer, A.: Memory-based spatio-temporal real-time object segmentation. In: Proceedings of the SPIE, International Symposium on Electronic Imaging, Conference on Real-Time Imaging (RTI), vol. 5012, pp. 10–21 (2003) 296_CR10 296_CR21 B. Cope (296_CR11) 2010; 59 M.K. Kundu (296_CR12) 2007; 76 296_CR20 S.B. Gray (296_CR7) 1971; 20 A. Pikaz (296_CR9) 1996; 29 296_CR1 296_CR2 296_CR3 O. Al-Kofahi (296_CR6) 2005; 14 296_CR4 L. Snidaro (296_CR22) 2003; 24 296_CR5 296_CR18 296_CR8 296_CR19 296_CR16 296_CR14 D. Iacoviello (296_CR17) 2007; 10 296_CR15 296_CR23 296_CR13 |
| References_xml | – reference: Ratnayake, K.; Amer, A.: An FPGA-based implementation of spatio-temporal object segmentation. In: Proceedings of the IEEE International Conference on Image Processing (ICIP), pp. 3265–3268 (2006) – reference: Li, W., Huading, J., Binjie, L.: A new binarization algorithm based on maximum gradient of histogram. In: Fourth International Conference on Image and Graphics (ICIG), pp. 368–371 (2007) – reference: Paul, L.R.: Thresholding for change detection. In: Sixth IEEE International Conference on Computer Vision, pp. 274–279 (1998) – reference: Berry, F., Chalimbaud, P.: Embedded active vision system based on FPGA architecture. EURASIP J.Embed. Syst. 12 (2007) – reference: Ashari, R.I., Hornsey, E.: FPGA implementation of real-time adaptive image thresholding. In: Proceedings of the SPIE, vol. 5578, pp. 410–419 (2004) – reference: Hesselbarth, S., Schunemann, T., Pirsch, P., Flatt, H., Blume, S.: A parallel hardware architecture for connected component labeling based on fast label merging. In: International Conference on Application-Specific systems, Architectures and Processors (ASAP 2008), pp. 144–149 (2008) – reference: Sutter, G., Dechamps, J.P., Bioul, G.: Synthesis of arithmetic circuits. Wiley Interscience Edition, Blackwell, London (2006) – reference: Rosin, P., Ellis, T.: Image difference threshold strategies and shadow detection. In: British Machine Vision Conference, pp. 347–356 (1995) – reference: Parhi, K.K.: VLSI digital signal processing systems, design and implementation. Blackwell, London (1999) – reference: Amer, A.: Memory-based spatio-temporal real-time object segmentation. In: Proceedings of the SPIE, International Symposium on Electronic Imaging, Conference on Real-Time Imaging (RTI), vol. 5012, pp. 10–21 (2003) – reference: IacovielloD.IacovielloF.SantisA.D.BartolomeoO.D.Optimal binarization of images by neural networks for morphological analysis of ductile cast ironPattern Anal Appl20071012513310.1007/s10044-006-0052-8 – reference: HOL.: Higher order logic theorem prover. http://hol.sourceforge.net/ Jun 2012 – reference: Abbasi, N., Athow, J., Amer, A.: Effect of mask size on the cost/performance of spatial property calculator. Appendix A in: A real-time FPGA architecture of a modified stable Euler-number algorithm for Image binarization, Department of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Canada, Technical Report vidpro-TR-01-12,http://users.encs.concordia.ca/amer/paper/report/SENA.pdf (2012) – reference: GrayS.B.Local properties of binary images in two dimensionsIEEE Transact Comput19712055156110.1109/T-C.1971.2232890216.50101 – reference: O’Gorman, L.: Binarization and multi-thresholding of document imnages using connectivity. In: Symposium on Document Analysis and Information Retrieval, pp. 237–252 (1994) – reference: Kundu, M.K., Murthy, C.A., Acharya, T., Bishnu, A., Bhattacharya, B.B.: On-chip computation of euler number of a binary image for efficient database search. In: Proceedings of the International Conference on Image Processing (ICIP), pp. 310–313 (2001) – reference: Owall, V., Hedberg, H., Kristensen, F.: Implementation of a labeling algorithm based on contour tracing with feature extraction. In: IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp. 1101–1104 (2007) – reference: Al-KofahiO.RoysamB.RadkeR.J.AndraS.Image change detection algorithms: a systematic surveyIEEE Transact Image Process20051429430710.1109/TIP.2004.8386982120664 – reference: CopeB.CheungP.LukW.HowesL.Performance comparison of graphics processors to reconfigurable logic: a case study Comput IEEE Transact201059443344810.1109/TC.2009.1792751812 – reference: SnidaroL.ForestiG.L.“Real-time thresholding with euler numbers”Pattern Recognition Letters2003241533154410.1016/S0167-8655(02)00392-61048.68122 – reference: PikazA.AverbuchA.Digital image thresholding based on topological stable statePattern Recognit19962982984310.1016/0031-3203(95)00126-3 – reference: KunduM.K.BishnuA.AcharyaT.DeyS.BhattacharyaB.B.A co-processor for computing the euler number of a binary image using divide-and-conquer strategyFundamenta Informaticae20077675891111.681412293051 – reference: Okuma, S., Yano, Y., Hashimiyama, T.: On-line filter generation for binary image processing using FPGA. In: Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics (SMC 99), vol. 5, pp. 565–570 (1999) – ident: 296_CR1 doi: 10.1109/ICIG.2007.15 – ident: 296_CR23 doi: 10.1117/12.477500 – ident: 296_CR10 doi: 10.5244/C.9.35 – ident: 296_CR15 – ident: 296_CR2 doi: 10.1155/2007/35010 – volume: 76 start-page: 75 year: 2007 ident: 296_CR12 publication-title: Fundamenta Informaticae doi: 10.3233/FUN-2007-761-206 – ident: 296_CR5 – ident: 296_CR13 doi: 10.1109/ASAP.2008.4580169 – ident: 296_CR8 – ident: 296_CR19 – ident: 296_CR16 doi: 10.1109/ICSMC.1999.815614 – ident: 296_CR18 – volume: 20 start-page: 551 year: 1971 ident: 296_CR7 publication-title: IEEE Transact Comput doi: 10.1109/T-C.1971.223289 – volume: 24 start-page: 1533 year: 2003 ident: 296_CR22 publication-title: Pattern Recognition Letters doi: 10.1016/S0167-8655(02)00392-6 – ident: 296_CR4 doi: 10.1117/12.566861 – ident: 296_CR20 doi: 10.1002/0471741426 – volume: 10 start-page: 125 year: 2007 ident: 296_CR17 publication-title: Pattern Anal Appl doi: 10.1007/s10044-006-0052-8 – volume: 29 start-page: 829 year: 1996 ident: 296_CR9 publication-title: Pattern Recognit doi: 10.1016/0031-3203(95)00126-3 – volume: 14 start-page: 294 year: 2005 ident: 296_CR6 publication-title: IEEE Transact Image Process doi: 10.1109/TIP.2004.838698 – ident: 296_CR14 doi: 10.1109/ISCAS.2007.378202 – ident: 296_CR3 doi: 10.1109/ICIP.2006.312920 – ident: 296_CR21 – volume: 59 start-page: 433 issue: 4 year: 2010 ident: 296_CR11 publication-title: Comput IEEE Transact doi: 10.1109/TC.2009.179 |
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