P-slice based efficient speculative multithreading

Microprocessor industry has recently shifted towards multi-core to take advantage of the ever increasing number of transistors provided by the new technologies. Unfortunately, the multi-core approach does not allow single threaded applications to benefit from the additional cores to improve their ex...

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Bibliographic Details
Published in:2009 International Conference on High Performance Computing (HiPC) pp. 119 - 128
Main Authors: Ranjan, R., Marcuello, P., Latorre, F., Gonzalez, A.
Format: Conference Proceeding
Language:English
Published: IEEE 01.12.2009
Subjects:
Algorithms
Computer architecture
Concurrent computing
Costs
Hardware
Multithreading
Parallel processing
Proposals
Runtime
Speculation
TLS
Yarn
ISBN:1424449227, 9781424449224
ISSN:1094-7256
Online Access:Get full text
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Summary:Microprocessor industry has recently shifted towards multi-core to take advantage of the ever increasing number of transistors provided by the new technologies. Unfortunately, the multi-core approach does not allow single threaded applications to benefit from the additional cores to improve their execution time. Speculative multithreading (SpMT) has been proposed in the past to boost performance of irregular applications in multi-core environments. In this work, we study the main bottlenecks of these architectures, such as the memory behavior and the pre-computation slices and propose two novel schemes that allow SpMT to get 25% average speedup over single threaded execution. We propose Selective Replication as a technique to improve the performance of the SpMT memory system. This technique does not introduce additional traffic in the bus and improves the performance of a conventional SpMT memory model by 6% on average and up to 21% for some applications. Also, we propose a scheme called Slice Specialization that reduces the number of instructions in the pre-computation slices by adapting the slice to every single speculative thread spawned. The later proposal outperforms previous schemes with slices by 15% and overall, both techniques combined achieve an improvement of 20% over a conventional SpMT processor.
ISBN:1424449227
9781424449224
ISSN:1094-7256
DOI:10.1109/HIPC.2009.5433216