On parallelization of circuit simulation SPICE3 using multithreaded programming techniques

With an enlarging community using electronic design automation, it is a prominent challenge to provide simulation program with integrated circuit emphasis (SPICE) users with sophisticated integrated circuit (IC) models, since many analog IC manufacturers provide software models in SPICE format. Mult...

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Bibliographic Details
Published in:Journal of the Chinese Institute of Engineers Vol. 35; no. 2; pp. 259 - 267
Main Authors: Weng, Tien-Hsiung, Perng, Ruey-Kuen, Li, Kuan-Ching
Format: Journal Article
Language:English
Published: Taylor & Francis Group 01.03.2012
Subjects:
circuit simulation
multithreaded
OpenMP
SPICE
ISSN:0253-3839, 2158-7299
Online Access:Get full text
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Summary:With an enlarging community using electronic design automation, it is a prominent challenge to provide simulation program with integrated circuit emphasis (SPICE) users with sophisticated integrated circuit (IC) models, since many analog IC manufacturers provide software models in SPICE format. Multi-core technology-based processors deliver better performance-to-cost ratios relative to their single-core predecessors through on-chip multithreading. In this article, we present a parallel version of a SPICE3 circuit simulator using two well-known shared-memory multithread programming interfaces. Two approaches in multithread programming has been considered and proposed to parallelize SPICE3 programs in shared-memory multiprocessor systems. Also, OpenMP and Pthreads libraries are considered to realize the proposed approaches that are used to redesign the SPICE3 device-loading functions. Case studies using SRAM circuits as input data were investigated. They consist of MOS devices modeled using BSIM3 models. Performance results from multi-core multiprocessor-based servers exhibit performance improvement of multithreaded implementation over the original version of SPICE3 circuit simulator.
ISSN:0253-3839
2158-7299
DOI:10.1080/02533839.2012.638537