Design and Implementation of Low Power, Area Crosstalk Reduction Using Static Timing Analysis

One of the biggest issues with VLSI connections is crosstalk, which is caused by coupling capacitance. Crosstalk reduces operation performance during switching activities and produces undesired output. Noise level rises as switching frequency does as well. Crosstalk will be eliminated by encode the...

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Published in:E3S web of conferences Vol. 540; p. 14001
Main Authors: Obulesu, Battari, Ashok, P., Rajesh, J., Madhu, K., Rakesh, G., Raghava Sarath Chandra Reddy, Guddety
Format: Journal Article Conference Proceeding
Language:English
Published: Les Ulis EDP Sciences 01.01.2024
Subjects:
bus decoder,very large scale integrated (vlsi)circuit
bus encoder
Capacitance
Computer engineering
Crosstalk
crosstalk probability detector
Design
Integrated circuits
Noise levels
Optimization
Optimization techniques
Power consumption
Static timing analysis
Wave division multiplexing
India
ISSN:2267-1242, 2555-0403, 2267-1242
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Abstract One of the biggest issues with VLSI connections is crosstalk, which is caused by coupling capacitance. Crosstalk reduces operation performance during switching activities and produces undesired output. Noise level rises as switching frequency does as well. Crosstalk will be eliminated by encode the data before connecting into the bus line. This procedure reduces the crosstalk issue by using the improved logic architecture. The proposed approach utilizes a combination of circuit-level optimization techniques, such as gate sizing and interconnect optimization, and advanced timing analysis tools to minimize power consumption and reduce crosstalk.
AbstractList One of the biggest issues with VLSI connections is crosstalk, which is caused by coupling capacitance. Crosstalk reduces operation performance during switching activities and produces undesired output. Noise level rises as switching frequency does as well. Crosstalk will be eliminated by encode the data before connecting into the bus line. This procedure reduces the crosstalk issue by using the improved logic architecture. The proposed approach utilizes a combination of circuit-level optimization techniques, such as gate sizing and interconnect optimization, and advanced timing analysis tools to minimize power consumption and reduce crosstalk.
Author Rakesh, G.
Obulesu, Battari
Ashok, P.
Rajesh, J.
Madhu, K.
Raghava Sarath Chandra Reddy, Guddety
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  fullname: Raghava Sarath Chandra Reddy, Guddety
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10.1109/TCAD.2005.852670
10.1016/j.vlsi.2005.08.006
10.1016/j.procs.2016.07.190
10.1109/ISQED.2009.4810378
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SubjectTerms bus decoder,very large scale integrated (vlsi)circuit
bus encoder
Capacitance
Computer engineering
Crosstalk
crosstalk probability detector
Design
Integrated circuits
Noise levels
Optimization
Optimization techniques
Power consumption
Static timing analysis
Wave division multiplexing
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