An efficient VLSI architecture for fast motion estimation by hybridizing parallel spiral and adaptive threshold star diamond search algorithm‐based search algorithm in HEVC

Summary This article proposes a high efficiency video coding (HEVC) standard hardware using block matching motion estimation algorithm. A hybrid parallel spiral and adaptive threshold star diamond search algorithm (Hyb PS‐ATSDSA) proposes for fast motion estimation in HEVC. Parallel spiral search ap...

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Vydáno v:Concurrency and computation Ročník 36; číslo 1
Hlavní autoři: Satheeskumar, R., Raghavaiah, Bonam, Geerthik, S., Senthil Kumar, T.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Hoboken, USA John Wiley & Sons, Inc 10.01.2024
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Témata:
Algorithms
block‐based matching algorithms (BMAs)
diamond adaptive‐rood‐pattern search (DARPS)
Diamonds
Field programmable gate arrays
Gate arrays
Matching
Motion simulation
parallel spiral search (PSS)
Search algorithms
Video compression
ISSN:1532-0626, 1532-0634
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Shrnutí:Summary This article proposes a high efficiency video coding (HEVC) standard hardware using block matching motion estimation algorithm. A hybrid parallel spiral and adaptive threshold star diamond search algorithm (Hyb PS‐ATSDSA) proposes for fast motion estimation in HEVC. Parallel spiral search approach utilizes spiral pattern for searching from center to the surroundings and adaptive threshold SDA consists of two phases, they are adaptive threshold and star diamond algorithm. To lower computational complexities in HEVC architecture, parallel spiral search algorithm uses several blocks matching schemes. Adaptive threshold and star diamond algorithm are used to reduce the matching errors and remove the invalid blocks early from the procedure of motion estimation and finally predicts the final motion of the image. Speed is increased while using this hybrid algorithm. Proposed structure is carried out in Xilinx; ISE 14.5 design suit, then the experimental outcomes are analyzed to existing motion estimation strategies in field‐programmable gate array devices. Experimental performance of the proposed Hyb‐PS‐ATSDSA‐ME‐HEVC method attains lower delay 33.97%, 32.97%, 62.97, and 26.97%, and lower area 34.867%, 45.97%, 27.97%, and 43.967% compared with the existing methods, such as FSA‐ME‐HEVC, TZSA‐ME‐HEVC, hyb TZSA‐IME‐HEVC, and IBMSA‐ME‐HEVC, respectively.
Bibliografie:Correction added on 31 August 2023, after first online publication: Fifth and Sixth authors and their affiliations were removed in this version.
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ISSN:1532-0626
1532-0634
DOI:10.1002/cpe.7873