FPGA-based Low Latency Square Root CORDIC Algorithm

The coordinate rotation digital computer (CORDIC) algorithm is a popular method used in many fields of science and technology. Unfortunately, it is a time-consuming process for central processing units (CPUs) and graphics processing units (GPUs), and even for specialized digital signal processing (D...

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Bibliographic Details
Published in:Journal of Telecommunications and Information Technology Vol. 99; no. 1; pp. 21 - 29
Main Authors: Węgrzyn, Mariusz, Voytusik, Stepan, Gavkalova, Nataliia
Format: Journal Article
Language:English
Published: Warsaw Instytut Lacznosci - Panstwowy Instytut Badawczy (National Institute of Telecommunications) 2025
National Institute of Telecommunications
Subjects:
Algorithms
Approximation
Central processing units
Computer vision
Control algorithms
CORDIC algorithm
CPUs
Digital computers
Digital filters
Digital signal processing
Edge computing
Field programmable gate arrays
Floating point arithmetic
FPGA
Graphics processing units
Lookup tables
Machine learning
Mathematical functions
Methods
Neural networks
Numerical analysis
numerical methods
reconfigurable computing systems
Signal processing
Telecommunications
ISSN:1509-4553, 1899-8852
Online Access:Get full text
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Summary:The coordinate rotation digital computer (CORDIC) algorithm is a popular method used in many fields of science and technology. Unfortunately, it is a time-consuming process for central processing units (CPUs) and graphics processing units (GPUs), and even for specialized digital signal processing (DSP) solutions. The CORDIC algorithm is an alternative for Newton-Raphson numerical calculation and for the FPGA based resource-expensive look-up-table (LUT) method. Various modifications of the CORDIC algorithm allow to speed up the operation of hardware in edge computing devices. With that context taken into consideration, this article presents a fast and accurate square root floating point (SQRT FP) CORDIC function which can be implemented in field programmable gate arrays (FPGAs). The proposed algorithm offers low-complexity, decent accuracy and speed, and is sufficient for digital signal processing (DSP) applications, such as digital filters, accelerators for neural networks, machine learning and computer vision applications, and intelligent robotic systems.
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ISSN:1509-4553
1899-8852
DOI:10.26636/jtit.2025.1.1950