SFD-resistant joint time-frequency symbol timing recovery algorithm and parallel FPGA implementation for broadband satellite communication

Existing symbol timing recovery (STR) algorithms face challenges in achieving a delicate balance between high throughput, high convergence accuracy, and robust resistance to sampling frequency deviation (SFD) while maintaining low complexity. For ultra-wideband single-carrier communication systems e...

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Veröffentlicht in:	Digital signal processing Jg. 160; S. 105051
Hauptverfasser:	Zhang, Peixin, Li, Guo, Gong, Fengkui, Zhang, Nan, Wang, Daqing, Li, Zhao
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Elsevier Inc 01.05.2025
Schlagworte:	Frequency-domain estimation Parallel FPGA Symbol timing recovery (STR) Time-domain interpolation Symbol timing recovery (STR) Frequency-domain estimation Parallel FPGA Time-domain interpolation
ISSN:	1051-2004
Online-Zugang:	Volltext
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