A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening

In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch circuit resistant to triple-node-upset (TNU) based on redundant-node hardening technology. This latch comprises eight 1P2N modules interlocked...

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Vydané v:IEEE transactions on very large scale integration (VLSI) systems Ročník 33; číslo 5; s. 1373 - 1383
Hlavní autori: Zhao, Qiang, Liu, Qingyi, Zhang, Xinyi, Hao, Licai, Li, Xin, Zhang, Shengyue, Peng, Chunyu, Lin, Zhiting, Wu, Xiulong
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.05.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
C-element (CE)
Delay
Delays
Fault tolerance
Hardening
high performance
high robustness
Inverters
Latches
Logic
Logic gates
low cost
Nodes
Power consumption
Power demand
Redundancy
Resists
Simulation
Tolerance analysis
Transistors
triple-node-upset (TNU)
Very large scale integration
ISSN:1063-8210, 1557-9999
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Popis
Shrnutí:In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch circuit resistant to triple-node-upset (TNU) based on redundant-node hardening technology. This latch comprises eight 1P2N modules interlocked, with its output isolated by two levels of C-elements (CEs), achieving tolerance to TNU. The performance of the redundant-node reinforcement TNU tolerant latch (RNRTTL) was simulated and verified using CMOS 65 nm technology. The simulation results indicate that the RNRTTL circuit has a D-Q delay of 14.14 ps, static power consumption of <inline-formula> <tex-math notation="LaTeX">4.03~\mu </tex-math></inline-formula>w, an area of <inline-formula> <tex-math notation="LaTeX">32.87~\mu </tex-math></inline-formula>m2, and an area-static power-D-Q delay-product (APDP) of 1873, respectively. Compared to the triple-node upset tolerant latches TTLL, TNU-latch, TNURL, and HLTNURL reported in the current literature, the proposed latch demonstrates an average reduction of 219.9%, 164.9%, 150.7%, and 2464.8% in D-Q delay, static power consumption, area, and APDP, respectively, indicating that the RNRTTL latch has superior comprehensive performance; furthermore, a series of 2000 Monte Carlo (MC) simulations on the node group <inline-formula> <tex-math notation="LaTeX">\langle </tex-math></inline-formula>Q, X0, X<inline-formula> <tex-math notation="LaTeX">8\rangle </tex-math></inline-formula> reveal that the proposed latch circuit possesses good stability, making it suitable for harsh radiation environments.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
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content type line 14
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2025.3535926