A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening

In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch circuit resistant to triple-node-upset (TNU) based on redundant-node hardening technology. This latch comprises eight 1P2N modules interlocked...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems Jg. 33; H. 5; S. 1373 - 1383
Hauptverfasser:	Zhao, Qiang, Liu, Qingyi, Zhang, Xinyi, Hao, Licai, Li, Xin, Zhang, Shengyue, Peng, Chunyu, Lin, Zhiting, Wu, Xiulong
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.05.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	C-element (CE) Delay Delays Fault tolerance Hardening high performance high robustness Inverters Latches Logic Logic gates low cost Nodes Power consumption Power demand Redundancy Resists Simulation Tolerance analysis Transistors triple-node-upset (TNU) Very large scale integration
ISSN:	1063-8210, 1557-9999
Online-Zugang:	Volltext
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