A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening

In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch circuit resistant to triple-node-upset (TNU) based on redundant-node hardening technology. This latch comprises eight 1P2N modules interlocked...

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Vydáno v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 33; číslo 5; s. 1373 - 1383
Hlavní autoři:	Zhao, Qiang, Liu, Qingyi, Zhang, Xinyi, Hao, Licai, Li, Xin, Zhang, Shengyue, Peng, Chunyu, Lin, Zhiting, Wu, Xiulong
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.05.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	C-element (CE) Delay Delays Fault tolerance Hardening high performance high robustness Inverters Latches Logic Logic gates low cost Nodes Power consumption Power demand Redundancy Resists Simulation Tolerance analysis Transistors triple-node-upset (TNU) Very large scale integration
ISSN:	1063-8210, 1557-9999
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Abstract	In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch circuit resistant to triple-node-upset (TNU) based on redundant-node hardening technology. This latch comprises eight 1P2N modules interlocked, with its output isolated by two levels of C-elements (CEs), achieving tolerance to TNU. The performance of the redundant-node reinforcement TNU tolerant latch (RNRTTL) was simulated and verified using CMOS 65 nm technology. The simulation results indicate that the RNRTTL circuit has a D-Q delay of 14.14 ps, static power consumption of <inline-formula> <tex-math notation="LaTeX">4.03~\mu </tex-math></inline-formula>w, an area of <inline-formula> <tex-math notation="LaTeX">32.87~\mu </tex-math></inline-formula>m2, and an area-static power-D-Q delay-product (APDP) of 1873, respectively. Compared to the triple-node upset tolerant latches TTLL, TNU-latch, TNURL, and HLTNURL reported in the current literature, the proposed latch demonstrates an average reduction of 219.9%, 164.9%, 150.7%, and 2464.8% in D-Q delay, static power consumption, area, and APDP, respectively, indicating that the RNRTTL latch has superior comprehensive performance; furthermore, a series of 2000 Monte Carlo (MC) simulations on the node group <inline-formula> <tex-math notation="LaTeX">\langle </tex-math></inline-formula>Q, X0, X<inline-formula> <tex-math notation="LaTeX">8\rangle </tex-math></inline-formula> reveal that the proposed latch circuit possesses good stability, making it suitable for harsh radiation environments.
AbstractList	In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch circuit resistant to triple-node-upset (TNU) based on redundant-node hardening technology. This latch comprises eight 1P2N modules interlocked, with its output isolated by two levels of C-elements (CEs), achieving tolerance to TNU. The performance of the redundant-node reinforcement TNU tolerant latch (RNRTTL) was simulated and verified using CMOS 65 nm technology. The simulation results indicate that the RNRTTL circuit has a D-Q delay of 14.14 ps, static power consumption of [Formula Omitted]w, an area of [Formula Omitted]m2, and an area-static power-D–Q delay-product (APDP) of 1873, respectively. Compared to the triple-node upset tolerant latches TTLL, TNU-latch, TNURL, and HLTNURL reported in the current literature, the proposed latch demonstrates an average reduction of 219.9%, 164.9%, 150.7%, and 2464.8% in D-Q delay, static power consumption, area, and APDP, respectively, indicating that the RNRTTL latch has superior comprehensive performance; furthermore, a series of 2000 Monte Carlo (MC) simulations on the node group [Formula Omitted]Q, X0, X[Formula Omitted] reveal that the proposed latch circuit possesses good stability, making it suitable for harsh radiation environments. In response to the issues of high cost, large overhead, and limited node fault tolerance in current latch hardening techniques, this article proposes a latch circuit resistant to triple-node-upset (TNU) based on redundant-node hardening technology. This latch comprises eight 1P2N modules interlocked, with its output isolated by two levels of C-elements (CEs), achieving tolerance to TNU. The performance of the redundant-node reinforcement TNU tolerant latch (RNRTTL) was simulated and verified using CMOS 65 nm technology. The simulation results indicate that the RNRTTL circuit has a D-Q delay of 14.14 ps, static power consumption of <inline-formula> <tex-math notation="LaTeX">4.03~\mu </tex-math></inline-formula>w, an area of <inline-formula> <tex-math notation="LaTeX">32.87~\mu </tex-math></inline-formula>m2, and an area-static power-D-Q delay-product (APDP) of 1873, respectively. Compared to the triple-node upset tolerant latches TTLL, TNU-latch, TNURL, and HLTNURL reported in the current literature, the proposed latch demonstrates an average reduction of 219.9%, 164.9%, 150.7%, and 2464.8% in D-Q delay, static power consumption, area, and APDP, respectively, indicating that the RNRTTL latch has superior comprehensive performance; furthermore, a series of 2000 Monte Carlo (MC) simulations on the node group <inline-formula> <tex-math notation="LaTeX">\langle </tex-math></inline-formula>Q, X0, X<inline-formula> <tex-math notation="LaTeX">8\rangle </tex-math></inline-formula> reveal that the proposed latch circuit possesses good stability, making it suitable for harsh radiation environments.
Author	Hao, Licai Zhao, Qiang Zhang, Xinyi Liu, Qingyi Wu, Xiulong Peng, Chunyu Zhang, Shengyue Lin, Zhiting Li, Xin
Author_xml	– sequence: 1 givenname: Qiang orcidid: 0000-0002-0278-5804 surname: Zhao fullname: Zhao, Qiang organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 2 givenname: Qingyi surname: Liu fullname: Liu, Qingyi organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 3 givenname: Xinyi surname: Zhang fullname: Zhang, Xinyi organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 4 givenname: Licai orcidid: 0000-0002-0637-5132 surname: Hao fullname: Hao, Licai organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 5 givenname: Xin orcidid: 0000-0002-0125-5254 surname: Li fullname: Li, Xin organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 6 givenname: Shengyue surname: Zhang fullname: Zhang, Shengyue organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 7 givenname: Chunyu orcidid: 0000-0003-2408-5048 surname: Peng fullname: Peng, Chunyu email: cyupeng@ahu.edu.cn organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 8 givenname: Zhiting orcidid: 0000-0002-3314-1606 surname: Lin fullname: Lin, Zhiting organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China – sequence: 9 givenname: Xiulong orcidid: 0000-0002-5012-2570 surname: Wu fullname: Wu, Xiulong organization: School of Integrated Circuits and Anhui Provincial High-Performance Integrated Circuit Engineering Research Center, Anhui University, Hefei, China
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SubjectTerms	C-element (CE) Delay Delays Fault tolerance Hardening high performance high robustness Inverters Latches Logic Logic gates low cost Nodes Power consumption Power demand Redundancy Resists Simulation Tolerance analysis Transistors triple-node-upset (TNU) Very large scale integration
Title	A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening
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