Devoge, P., Aziza, H., Lorenzini, P., Masson, P., Malherbe, A., Julien, F., . . . Niel, S. (2023). Device and circuit-level evaluation of a zero-cost transistor architecture developed via process optimization. Solid-state electronics, 201, 108575. https://doi.org/10.1016/j.sse.2022.108575
Chicago-Zitierstil (17. Ausg.)Devoge, Paul, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Regnier, und Stephan Niel. "Device and Circuit-level Evaluation of a Zero-cost Transistor Architecture Developed via Process Optimization." Solid-state Electronics 201 (2023): 108575. https://doi.org/10.1016/j.sse.2022.108575.
MLA-Zitierstil (9. Ausg.)Devoge, Paul, et al. "Device and Circuit-level Evaluation of a Zero-cost Transistor Architecture Developed via Process Optimization." Solid-state Electronics, vol. 201, 2023, p. 108575, https://doi.org/10.1016/j.sse.2022.108575.