Single Event Transient Characterization of a Low-Dropout Regulator in a Sub-20 nm CMOS Technology

In this article, the mechanism of single event transient (SET) of a low-dropout (LDO) regulator fabricated in a sub-20 nm fin-field effect transistor (FinFET) technology was studied. Simulation program with integrated circuit emphasis (SPICE) circuit simulation finds that the most sensitive nodes ar...

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Veröffentlicht in:IEEE transactions on nuclear science Jg. 72; H. 10; S. 3351 - 3363
Hauptverfasser: Wang, Xun, Chen, Jianjun, Liang, Bin, Wen, Yi, Shen, Fan, Chi, Yaqing, Luo, Deng, Yu, Guofang
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.10.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Circuit simulation
Confidence intervals
Field effect transistors
FinFETs
Heavy ion experiment
Heavy ions
Hypothesis testing
Integrated circuits
Ions
Logic gates
low-dropout (LDO) regulator
Power consumption
Pulse amplitude
Pulse duration
Radiation hardening
Regulation
Regulators
Reinforcement
Semiconductor devices
Simulation
simulation program with integrated circuit emphasis (SPICE) circuit simulation
single event transient (SET)
SPICE
Statistical analysis
sub-20 nm fin-field effect transistor (FinFET) process
Transistors
Voltage control
ISSN:0018-9499, 1558-1578
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Zusammenfassung:In this article, the mechanism of single event transient (SET) of a low-dropout (LDO) regulator fabricated in a sub-20 nm fin-field effect transistor (FinFET) technology was studied. Simulation program with integrated circuit emphasis (SPICE) circuit simulation finds that the most sensitive nodes are inside the error amplifier (EA) and bandgap reference (BGR). Moreover, the mechanism of generating SET was also studied. Furthermore, the SET characteristics of the LDO test chip were further studied through heavy ion experiments. The result of the SET width and amplitude statistical distribution found in the experiment is consistent with the SPICE circuit simulation result by histogram analysis, confidence interval, and hypothesis testing, which confirms the conclusion of the SPICE circuit simulation through a view of statistics. Based on the above analysis results, a radiation-hardened LDO was also proposed based on a comparator and pump transistor, focusing on the output of EA. In a positive SET pulse situation, the pulsewidth before and after the reinforcement is 55.83% shorter. The pulse amplitude is reduced by 91.37% through SPICE circuit simulation; in negative SET pulse situation, the pulsewidth before and after the reinforcement is 35.25% shorter, and the pulse amplitude is reduced by 78.30%; in BGR output situation, the pulsewidth before and after the reinforcement is 55.83% shorter, and the pulse amplitude is reduced by 91.37%; finally, through the analysis of power consumption and area calculation before and after hardening, the effectiveness of the hardening design was verified.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2025.3598057