High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm

A multiply-accumulator, often abbreviated as a MAC unit, is central to a multitude of computational tasks, particularly those tasks (such as neural networks) involving array-based mathematical computations. The quest for novel methods to efficiently store and process data in a MAC has become imperat...

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Vydané v:IEEE transactions on circuits and systems. I, Regular papers Ročník 72; číslo 7; s. 3258 - 3271
Hlavní autori: Wen, Wanting, Zhao, Guangchao, Hu, Wanbo, Li, Ziye, Wang, Xingli, Friedman, Eby G., Tay, Beng Kang, Ke, Shaolin, Huang, Mingqiang
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.07.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Accumulators
Accuracy
Adders
Algorithms
Approximation algorithms
Circuits
CNTFETs
Encoding
Field effect transistors
multiplying-accumulator
Multivalued logic
Neural networks
Performance evaluation
Power management
Semiconductor devices
Ternary logic circuit
Threshold voltage
Transistors
Vector processing (computers)
ISSN:1549-8328, 1558-0806
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Popis
Shrnutí:A multiply-accumulator, often abbreviated as a MAC unit, is central to a multitude of computational tasks, particularly those tasks (such as neural networks) involving array-based mathematical computations. The quest for novel methods to efficiently store and process data in a MAC has become imperative. Recently, ternary logic has attracted significant attention due to its higher information density than conventional binary systems. However, though numerous studies have showcased ternary arithmetic circuits, advancements in ternary-based vector processing have been notably scarce. To bridge this gap, this work undertakes comprehensive study into the optimization of ternary MAC units. Firstly, we propose various ternary approximate algorithms which shows 30%-less power consumption and only 2% computation error when compared with the accurate design. Secondly, we design sophisticated ternary circuits and obtain 74%~80% lower power-delay-product (PDP) than previous works. Finally, we evaluate the proposed ternary MAC unit using both carbon-nanotube field-effect transistor (CNTFET) and silicon-based 180 nm CMOS processes. The simulation results show the ternary circuit is better than binary circuit in terms of both area (~45% less) and power (~30% less), highlighting its strong potential for practical applications.
Bibliografia:ObjectType-Article-1
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content type line 14
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2024.3492797