Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece

Classic McEliece, with a remarkably stable security level, has been selected as one of the four key-establishment algorithms in the fourth-round evaluation of the post-quantum cryptography (PQC) standardization process of national institute of standards and technology (NIST). However, its memory-int...

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Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 72; no. 3; pp. 1321 - 1331
Main Authors: Zhang, Haochen, Qiao, Xinyuan, Tian, Jing, Song, Suwen, Wang, Zhongfeng
Format: Journal Article
Language:English
Published: New York IEEE 01.03.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Architecture
classic McEliece
code-based cryptography
Codes
Computer architecture
Computer memory
Electronic mail
Fanout
FPGA
Gauss elimination
Gaussian elimination
Generators
Hardware
hardware implementation
National security
Optimization
Polynomials
PQC
Public key
Quantum cryptography
Resource scheduling
Systematics
Systolic arrays
ISSN:1549-8328, 1558-0806
Online Access:Get full text
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Summary:Classic McEliece, with a remarkably stable security level, has been selected as one of the four key-establishment algorithms in the fourth-round evaluation of the post-quantum cryptography (PQC) standardization process of national institute of standards and technology (NIST). However, its memory-intensive and time-consuming key generation poses an obstacle to widespread use. In this paper, we propose a fast hardware implementation of the key generation incorporating several architectural optimizations. For the Gaussian elimination, we optimize the scheduling of computing resources and the memory access process and present a high-performance and flexible systemizer with multiple low fan-out systolic arrays. Besides, an algorithmic-level parallelized design for entry generation and Gaussian elimination is proposed to reduce the redundant computation time. A compact entry generator with a multi-level feedback mechanism and a 2-D high-speed FFT module facilitates continuous streaming the generated entries into the systemizer.FPGA implementation results show that our designs for the key generation improve time-area efficiency by 11.9% to 43.2% compared to the state-of-the-arts. Moreover, compared to the hardware implementations for the key generation of the other two quasi-cyclic code-based PQC algorithms, ours for Classic McEliece based on the random code achieves close to or better results in several metrics.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2025.3528119