A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture

The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient and programmable implementations of Error Correction Codes (ECC) and decoders. The...

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Bibliographic Details

Published in:	IEEE transactions on computer-aided design of integrated circuits and systems Vol. 42; no. 12; p. 1
Main Authors:	Hassan, Sahil, Dattilo, Parker, Akoglu, Ali
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.12.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Computer architecture Decoders Decoding Energy consumption Error correction Error correction codes FPGA based emulation Gallager-B Internet of Things Machine learning Mathematical models Neuromorphic computing Neuromorphics Neurons
ISSN:	0278-0070, 1937-4151
Online Access:	Get full text
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