Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict...

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Published in:	IEEE transactions on circuits and systems. I, Regular papers Vol. 61; no. 5; pp. 1376 - 1389
Main Authors:	Guohui Wang, Hao Shen, Yang Sun, Cavallaro, Joseph R., Vosoughi, Aida, Yuanbin Guo
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.05.2014 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Architecture ASIC implementation Circuits Clocks CMOS Computer architecture Concurrent processing Decoders Decoding Hardware HSPA interleaver Long Term Evolution LTE/LTE-advanced memory contention parallel processing Throughput turbo decoder VLSI architecture Wireless communication Wireless communications
ISSN:	1549-8328, 1558-0806
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Abstract	To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA +/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2 . When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.
AbstractList	To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA +/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2 . When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards. To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA[Formula Omitted]/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm[Formula Omitted]. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.
Author	Vosoughi, Aida Yuanbin Guo Yang Sun Cavallaro, Joseph R. Hao Shen Guohui Wang
Author_xml	– sequence: 1 surname: Guohui Wang fullname: Guohui Wang email: wgh@rice.edu organization: Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA – sequence: 2 surname: Hao Shen fullname: Hao Shen organization: Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA – sequence: 3 surname: Yang Sun fullname: Yang Sun organization: Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA – sequence: 4 givenname: Joseph R. surname: Cavallaro fullname: Cavallaro, Joseph R. organization: Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA – sequence: 5 givenname: Aida surname: Vosoughi fullname: Vosoughi, Aida organization: Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA – sequence: 6 surname: Yuanbin Guo fullname: Yuanbin Guo organization: Wireless R&D, US Res. Center, Plano, TX, USA
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Cites_doi	10.1109/TIT.2004.833353 10.1109/JSSC.2008.2007166 10.1109/TIT.2005.864442 10.1109/TVLSI.2002.808451 10.1109/TCOMM.2011.092011.100157 10.7873/DATE.2013.036 10.1109/JSSC.2010.2075390 10.1145/2206781.2206819 10.1016/j.vlsi.2010.07.001 10.1007/s11265-010-0521-6 10.1109/TSP.2013.2264057 10.1109/TCSII.2008.919510 10.1109/TVLSI.2007.899237 10.1109/TIT.2012.2190492 10.1109/TCSII.2007.895313 10.1109/DATE.2007.364668 10.1109/ISCAS.2013.6572102 10.1109/CICC.2009.5280790 10.1023/B:VLSI.0000047272.75049.0e 10.1007/s11265-013-0735-5 10.1109/TVLSI.2009.2032553 10.1109/ICCS.2010.5686499 10.1109/ReConFig.2009.16 10.1049/el:20001357 10.1109/TIT.2005.864450 10.1109/ISCAS.2005.1464950 10.1109/TCOMM.2008.050502 10.1109/ICC.2012.6364909 10.1109/ICC.2004.1312507 10.1109/JSSC.2009.2038428 10.1109/ICC.1993.397441 10.1109/DSD.2004.1333294 10.1109/ISSCC.2003.1234245 10.1049/el:20020148 10.1109/ISCAS.2002.1009986
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References	ref35 ref13 vosoughi (ref40) 2013 ref37 ref15 ref31 ref30 ref33 ref11 ref32 ref10 (ref3) 2012 ref1 ref39 ref17 ref38 ref19 ref18 belfanti (ref24) 2013 salmela (ref12) 2007 ref45 ref23 (ref4) 2012 ref26 ref25 may (ref14) 2010 ref20 ref42 ref22 ref44 ref21 ref43 ref28 ref27 (ref2) 2012 ref29 wang (ref16) 2011 ref8 ref7 ryu (ref41) 2006; 52 ref9 eid (ref34) 2011 ref6 ref5 nieminen (ref36) 2013; pp
References_xml	– year: 2012 ident: ref3 article-title: Evolved universal terrestrial radio access (E-UTRA); multiplexing and channel coding, Tech. Spec. 36.212 release-11 – volume: pp start-page: 1 year: 2013 ident: ref36 article-title: A contention-free parallel access by butterfly networks for turbo interleavers publication-title: IEEE Trans Inf Theory – ident: ref28 doi: 10.1109/TIT.2004.833353 – ident: ref9 doi: 10.1109/JSSC.2008.2007166 – volume: 52 start-page: 1254 year: 2006 ident: ref41 article-title: On quadratic inverses for quadratic permutation polynomials over integer rings publication-title: IEEE Trans Inf Theory doi: 10.1109/TIT.2005.864442 – ident: ref7 doi: 10.1109/TVLSI.2002.808451 – ident: ref45 doi: 10.1109/TCOMM.2011.092011.100157 – ident: ref23 doi: 10.7873/DATE.2013.036 – ident: ref17 doi: 10.1109/JSSC.2010.2075390 – ident: ref35 doi: 10.1145/2206781.2206819 – ident: ref19 doi: 10.1016/j.vlsi.2010.07.001 – ident: ref20 doi: 10.1007/s11265-010-0521-6 – year: 2012 ident: ref4 article-title: HSPA<formula formulatype="inline"><tex Notation="TeX">$+$</tex></formula> Advanced taking HSPA<formula formulatype="inline"><tex Notation="TeX">$+$</tex></formula> to the next level – ident: ref21 doi: 10.1109/TSP.2013.2264057 – start-page: 831 year: 2007 ident: ref12 article-title: Efficient parallel memory organization for turbo decoders publication-title: Proc Eur Signal Process Conf – ident: ref13 doi: 10.1109/TCSII.2008.919510 – ident: ref37 doi: 10.1109/TVLSI.2007.899237 – year: 2012 ident: ref2 article-title: Technical specification group radio access network; multiplexing and channel coding (FDD), tech. spec. 25.212 release-11 – ident: ref42 doi: 10.1109/TIT.2012.2190492 – ident: ref22 doi: 10.1109/TCSII.2007.895313 – start-page: 284c year: 2013 ident: ref24 article-title: A 1 Gbps LTE-advanced turbo-decoder ASIC in 65 nm CMOS publication-title: Proc VLSI Symp – ident: ref32 doi: 10.1109/DATE.2007.364668 – ident: ref1 doi: 10.1109/ISCAS.2013.6572102 – start-page: 2701 year: 2011 ident: ref34 article-title: Memory conflict analysis for a multi-standard, reconfigurable turbo decoder publication-title: Proc ISCAS – ident: ref38 doi: 10.1109/CICC.2009.5280790 – ident: ref11 doi: 10.1023/B:VLSI.0000047272.75049.0e – ident: ref39 doi: 10.1007/s11265-013-0735-5 – ident: ref18 doi: 10.1109/TVLSI.2009.2032553 – start-page: 1420 year: 2010 ident: ref14 article-title: A 150 Mbit/s 3GPP LTE turbo code decoder publication-title: Proc DATE – ident: ref10 doi: 10.1109/ICCS.2010.5686499 – ident: ref44 doi: 10.1109/ReConFig.2009.16 – ident: ref43 doi: 10.1049/el:20001357 – ident: ref31 doi: 10.1109/TIT.2005.864450 – ident: ref30 doi: 10.1109/ISCAS.2005.1464950 – start-page: 113 year: 2011 ident: ref16 article-title: Concurrent interleaver architecture for high throughput multi-standard parallel turbo decoder publication-title: Proc IEEE Int Conf ASAP – ident: ref33 doi: 10.1109/TCOMM.2008.050502 – ident: ref5 doi: 10.1109/ICC.2012.6364909 – ident: ref29 doi: 10.1109/ICC.2004.1312507 – ident: ref15 doi: 10.1109/JSSC.2009.2038428 – ident: ref6 doi: 10.1109/ICC.1993.397441 – ident: ref27 doi: 10.1109/DSD.2004.1333294 – ident: ref8 doi: 10.1109/ISSCC.2003.1234245 – ident: ref25 doi: 10.1049/el:20020148 – start-page: 356 year: 2013 ident: ref40 article-title: Highly scalable on-the-fly interleaved address generation for UMTS/HSPA<formula formulatype="inline"><tex Notation="TeX">$+$</tex></formula> parallel turbo decoder publication-title: Proc IEEE Int Conf ASAP – ident: ref26 doi: 10.1109/ISCAS.2002.1009986
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SubjectTerms	Architecture ASIC implementation Circuits Clocks CMOS Computer architecture Concurrent processing Decoders Decoding Hardware HSPA interleaver Long Term Evolution LTE/LTE-advanced memory contention parallel processing Throughput turbo decoder VLSI architecture Wireless communication Wireless communications
Title	Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder
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