Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 61; no. 5; pp. 1376 - 1389
Main Authors: Guohui Wang, Hao Shen, Yang Sun, Cavallaro, Joseph R., Vosoughi, Aida, Yuanbin Guo
Format: Journal Article
Language:English
Published: New York IEEE 01.05.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Architecture
ASIC implementation
Circuits
Clocks
CMOS
Computer architecture
Concurrent processing
Decoders
Decoding
Hardware
HSPA
interleaver
Long Term Evolution
LTE/LTE-advanced
memory contention
parallel processing
Throughput
turbo decoder
VLSI architecture
Wireless communication
Wireless communications
ISSN:1549-8328, 1558-0806
Online Access:Get full text
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Summary:To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA +/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2 . When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2014.2309810