Runahead Threads to improve SMT performance

In this paper, we propose runahead threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in simultaneous multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under lo...

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Veröffentlicht in:2008 IEEE 14th International Symposium on High Performance Computer Architecture S. 149 - 158
Hauptverfasser: Ramirez, T., Pajuelo, A., Santana, O.J., Valero, M.
Format: Tagungsbericht Verlag
Sprache:Englisch
Veröffentlicht: IEEE 01.02.2008
Institute of Electrical and Electronics Engineers (IEEE)
Schlagworte:
Arquitectura de computadors
Disseny
Informàtica
Multi-threading
Parallel processing
Parallel processing (Electronic computers)
Prefetching
Processament en paral·lel (Ordinadors)
Program processors
Programari
Proposals
Registers
Resource allocation
Resource management
Simultaneous multithreading processors
Software architecture
Storage management
Throughput
Àrees temàtiques de la UPC
ISBN:1424420709, 9781424420704
ISSN:1530-0897
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Beschreibung
Zusammenfassung:In this paper, we propose runahead threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in simultaneous multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under long-latency blocking memory operations. These speculative threads prefetch data and instructions with minimal resources, reducing critical resource conflicts between threads. We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies. In terms of throughput and fairness, our results show that RaT performs better than any other policy. The proposed mechanism improves average throughput by 37% regarding previous static fetch policies and by 28% compared to previous dynamic resource scheduling mechanisms. RaT also improves fairness by 36% and 30% respectively. In addition, the proposed mechanism permits register file size reduction of up to 60% in a SMT processor without performance degradation.
ISBN:1424420709
9781424420704
ISSN:1530-0897
DOI:10.1109/HPCA.2008.4658635