Runahead Threads to improve SMT performance
In this paper, we propose runahead threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in simultaneous multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under lo...
Uložené v:
| Vydané v: | 2008 IEEE 14th International Symposium on High Performance Computer Architecture s. 149 - 158 |
|---|---|
| Hlavní autori: | , , , |
| Médium: | Konferenčný príspevok.. Publikácia |
| Jazyk: | English |
| Vydavateľské údaje: |
IEEE
01.02.2008
Institute of Electrical and Electronics Engineers (IEEE) |
| Predmet: | |
| ISBN: | 1424420709, 9781424420704 |
| ISSN: | 1530-0897 |
| On-line prístup: | Získať plný text |
| Tagy: |
Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
|
| Abstract | In this paper, we propose runahead threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in simultaneous multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under long-latency blocking memory operations. These speculative threads prefetch data and instructions with minimal resources, reducing critical resource conflicts between threads. We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies. In terms of throughput and fairness, our results show that RaT performs better than any other policy. The proposed mechanism improves average throughput by 37% regarding previous static fetch policies and by 28% compared to previous dynamic resource scheduling mechanisms. RaT also improves fairness by 36% and 30% respectively. In addition, the proposed mechanism permits register file size reduction of up to 60% in a SMT processor without performance degradation. |
|---|---|
| AbstractList | In this paper, we propose runahead threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in simultaneous multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under long-latency blocking memory operations. These speculative threads prefetch data and instructions with minimal resources, reducing critical resource conflicts between threads. We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies. In terms of throughput and fairness, our results show that RaT performs better than any other policy. The proposed mechanism improves average throughput by 37% regarding previous static fetch policies and by 28% compared to previous dynamic resource scheduling mechanisms. RaT also improves fairness by 36% and 30% respectively. In addition, the proposed mechanism permits register file size reduction of up to 60% in a SMT processor without performance degradation. In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT) processors. Our technique converts a resource intensive memory-bound thread to a speculative light thread under long-latency blocking memory operations. These speculative threads prefetch data and instructions with minimal resources, reducing critical resource conflicts between threads. We compare an SMT architecture using RaT to both state-of-the-art static fetch policies and dynamic resource control policies. In terms of throughput and fairness, our results show that RaT performs better than any other policy. The proposed mechanism improves average throughput by 37% regarding previous static fetch policies and by 28% compared to previous dynamic resource scheduling mechanisms. RaT also improves fairness by 36% and 30% respectively. In addition, the proposed mechanism permits register file size reduction of up to 60% in a SMT processor without performance degradation. Peer Reviewed |
| Author | Santana, O.J. Pajuelo, A. Valero, M. Ramirez, T. |
| Author_xml | – sequence: 1 givenname: T. surname: Ramirez fullname: Ramirez, T. organization: Univ. Politelecnica de Catalunya, Barcelona – sequence: 2 givenname: A. surname: Pajuelo fullname: Pajuelo, A. organization: Univ. Politelecnica de Catalunya, Barcelona – sequence: 3 givenname: O.J. surname: Santana fullname: Santana, O.J. organization: Univ. de Las Palmas de Gran Canaria, Las Palmas de Gran Canaria – sequence: 4 givenname: M. surname: Valero fullname: Valero, M. organization: Univ. Politelecnica de Catalunya, Barcelona – sequence: 5 givenname: M. surname: Valero fullname: Valero, M. organization: Barcelona Supercomput. Center, Barcelona |
| BookMark | eNpFUF1Lw0AQPLAF29ofIL7kXRL3PvYu91iCWqGiaHwO1-sdjZgPLq3gv--FFlxYhoGZZWbnZNJ2rSPklkJGKeiH9XuxyhhAngmJueR4ReZUMCEYKNATMqPIIYVcqymZjzoNwBGvyXIYviGOQC4Fzsj9x7E1e2d2SbkPEYbk0CV104fu1yWfr2XSu-C70JjWuhsy9eZncMsLLsjX02NZrNPN2_NLsdqklgmKqZDUCi2VwZwztfNotZTbSD1jMavXWlHjVW7oFtnYRmunqZIxE3LOgS8IPd-1w9FWwVkXrDlUnan_ybixK6uYFhxGz93ZUzvnqj7UjQl_1eU5_ATLr1P8 |
| ContentType | Conference Proceeding Publication |
| Contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| Contributor_xml | – sequence: 1 fullname: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors – sequence: 2 fullname: Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| Copyright | info:eu-repo/semantics/openAccess |
| Copyright_xml | – notice: info:eu-repo/semantics/openAccess |
| DBID | 6IE 6IL CBEJK RIE RIL XX2 |
| DOI | 10.1109/HPCA.2008.4658635 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Xplore POP ALL IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present Recercat |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EndPage | 158 |
| ExternalDocumentID | oai_recercat_cat_2072_294300 4658635 |
| Genre | orig-research |
| GroupedDBID | 29O 6IE 6IF 6IH 6IK 6IL 6IM 6IN AAJGR AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IPLJI M43 OCL RIE RIL RNS AARBI IERZE RIB RIC XX2 |
| ID | FETCH-LOGICAL-c2415-461c4967a58327df5c966b7a5f22586f9971af78a1b52110999e9176045533303 |
| IEDL.DBID | RIE |
| ISBN | 1424420709 9781424420704 |
| ISSN | 1530-0897 |
| IngestDate | Fri Nov 07 13:45:06 EST 2025 Wed Aug 27 02:02:49 EDT 2025 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | true |
| LCCN | 2008900355 |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c2415-461c4967a58327df5c966b7a5f22586f9971af78a1b52110999e9176045533303 |
| OpenAccessLink | https://recercat.cat/handle/2072/294300 |
| PageCount | 10 |
| ParticipantIDs | ieee_primary_4658635 csuc_recercat_oai_recercat_cat_2072_294300 |
| PublicationCentury | 2000 |
| PublicationDate | 2008-02 |
| PublicationDateYYYYMMDD | 2008-02-01 |
| PublicationDate_xml | – month: 02 year: 2008 text: 2008-02 |
| PublicationDecade | 2000 |
| PublicationTitle | 2008 IEEE 14th International Symposium on High Performance Computer Architecture |
| PublicationTitleAbbrev | HPCA |
| PublicationYear | 2008 |
| Publisher | IEEE Institute of Electrical and Electronics Engineers (IEEE) |
| Publisher_xml | – name: IEEE – name: Institute of Electrical and Electronics Engineers (IEEE) |
| SSID | ssj0000453645 ssj0002951 |
| Score | 1.9124254 |
| Snippet | In this paper, we propose runahead threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in... In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in... |
| SourceID | csuc ieee |
| SourceType | Open Access Repository Publisher |
| StartPage | 149 |
| SubjectTerms | Arquitectura de computadors Disseny Informàtica Multi-threading Parallel processing Parallel processing (Electronic computers) Prefetching Processament en paral·lel (Ordinadors) Program processors Programari Proposals Registers Resource allocation Resource management Simultaneous multithreading processors Software architecture Storage management Throughput Àrees temàtiques de la UPC |
| Title | Runahead Threads to improve SMT performance |
| URI | https://ieeexplore.ieee.org/document/4658635 https://recercat.cat/handle/2072/294300 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV07a8MwEBZJ6NCpj6T0jYZObd3YjmTZYwkNWRpCm0I2c3pBFickdn9_T7biUOjSwWAZg81Jd9-9j5AHFVoEVkAjRwILGJdpAEkEQZTYNLFg9EiyetiEmM3S5TKbd8hzWwtjjKmTz8yLu61j-XqtKucqGzKESwTILukKIZpardafgqpJE1HzUjjOuO-V6vK1XPu_pqgrxjOe7Xs9-TXz4c4ozIbT-fi1SbH0X0NZrXaV-jV9pQafycn_fvuUDA5VfHTe4tMZ6ZjinJzsxzhQz9V98vRRFYAyWdMFbizoHS3XdFU7Gwz9fF_QzaG4YEC-Jm-L8TTwMxQC5bA5YEmkWJYI4Mi6Qluu0L6RuLTIyLgbWSYisCKFSHJnC6K-aNCCS5CcqAgivl2QXrEuzCWhMrYcgIXappzJkZao3ZgRNwykEQLCK_LoCJWjpDZbBWXuOle3C3chreM8dg3f8eW-I1S-aXpq5J5G138_viHHTZ6GSyO5Jb1yW5k7cqS-y9Vue18fhB9DxalF |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NS8MwFH_MKehp6iZ-m4Mnta7tkn4cZTgmbmNohd1Kkiawyza21r_flzbrELx4KDSl0PKS937v-wHcS1cjsHI0cgSnDmUicnjgcccLdBRorrKeoOWwiXAyiWazeNqAp7oWRilVJp-pZ3NbxvKzpSyMq6xLES4RIPdgn1Hqe1W1Vu1RQeWkiqlZOezHzHZLNRlbpgFgVdbl4ymPt92e7JragKfnxt3htP9SJVna76G0lptC_pq_UsLPoPW_Hz-Gzq6Oj0xrhDqBhlqcQms7yIFYvm7D40ex4CiVM5Lg1vJsQ_IlmZfuBkU-xwlZ7coLOvA1eE36Q8dOUXCkQWeHBp6kcRByhswbZppJtHAELjWyMu5HHIce12HEPcGMNYgao0IbLkByoiqICHcGzcVyoc6BCF8zzqmb6YhR0csE6jeqxxTlQoUhdy_gwRAqRVmt1pLnqeldXS_MhbT2U9-0fMeX24ZQ6arqqpFaGl3-_fgODofJeJSO3ibvV3BUZW2YpJJraObrQt3AgfzO55v1bXkofgBLs6yM |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2008+IEEE+14th+International+Symposium+on+High+Performance+Computer+Architecture&rft.atitle=Runahead+Threads+to+improve+SMT+performance&rft.au=Ramirez%2C+T.&rft.au=Pajuelo%2C+A.&rft.au=Santana%2C+O.J.&rft.au=Valero%2C+M.&rft.date=2008-02-01&rft.pub=IEEE&rft.isbn=9781424420704&rft.issn=1530-0897&rft.spage=149&rft.epage=158&rft_id=info:doi/10.1109%2FHPCA.2008.4658635&rft.externalDocID=4658635 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1530-0897&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1530-0897&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1530-0897&client=summon |

