Redesignability check for analog circuits with incomplete implementation information
Reengineering of electronic circuits has received considerable interest in the design automation community. Reengineering is the examination and alternation of a system to reconstitute it in a new form, which potentially involves changes at the requirements, design, and implementation level. This pa...
Uložené v:
| Vydané v: | IEEE transactions on circuits and systems. 1, Fundamental theory and applications Ročník 46; číslo 8; s. 939 - 949 |
|---|---|
| Hlavní autori: | , |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
New York, NY
IEEE
01.08.1999
Institute of Electrical and Electronics Engineers |
| Predmet: | |
| ISSN: | 1057-7122 |
| On-line prístup: | Získať plný text |
| Tagy: |
Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
|
| Abstract | Reengineering of electronic circuits has received considerable interest in the design automation community. Reengineering is the examination and alternation of a system to reconstitute it in a new form, which potentially involves changes at the requirements, design, and implementation level. This paper deals with the redesign problem in which the original implementation information is either missing or incomplete. Given a target circuit with a set of test points and a set of missing components, a circuit is redesignable if the transfer function of each missing component can be derived from the partial knowledge in existing implementation. The derived transfer functions are then used to construct the missing components. This paper presents an efficient algorithm that checks if a target circuit is redesignable. A set of check rules is developed from circuit topology without the need of circuit simulations. Thus, the redesignability check process can be applied for both linear and nonlinear circuits. |
|---|---|
| AbstractList | Reengineering of electronic circuits has received considerable interest in the design automation community. Reengineering is the examination and alternation of a system to reconstitute it in a new form, which potentially involves changes at the requirements, design, and implementation level. This paper deals with the redesign problem in which the original implementation information is either missing or incomplete. Given a target circuit with a set of test points and a set of missing components, a circuit is redesignable if the transfer function of each missing component can be derived from the partial knowledge in existing implementation. The derived transfer functions are then used to construct the missing components. This paper presents an efficient algorithm that checks if a target circuit is redesignable. A set of check rules is developed from circuit topology without the need of circuit simulations. Thus, the redesignability check process can be applied for both linear and nonlinear circuits. |
| Author | Wei-Hsing Huang Chin-Long Wey |
| Author_xml | – sequence: 1 givenname: C.-L surname: WEY fullname: WEY, C.-L organization: Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI 48824-1226, United States – sequence: 2 givenname: W.-H surname: HUANG fullname: HUANG, W.-H organization: Mentor Graphics, Wilsonville, OR 97070, United States |
| BackLink | http://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=1918578$$DView record in Pascal Francis |
| BookMark | eNpF0D1PwzAQBmAPRaItDKxMHlgYUmzHiZ0RVXxJlZBQmSPnbLeGxIlsI9R_T0oqmN6T7rkb3gWa-d4bhK4oWVFKqjtJV0KSXBQzNKekEJmgjJ2jRYwfhFAuuZyj7ZvRJrqdV41rXTpg2Bv4xLYPWHnV9jsMLsCXSxF_u7THzkPfDa1JBrtjdsYnlVzvx8141P3OF-jMqjaay1Mu0fvjw3b9nG1en17W95sMWF6kjAsJIISVhRa6KnmhCdXa8oZxChokWEG4lLlujLZQNkxVpVCsYiwHq3KbL9HN9HdQEVRrg_LgYj0E16lwqGlFZSHkyG4nBqGPMRj7L0h9bKqWtJ6aGu31ZJ0x5s-dlj_EdGmJ |
| CODEN | ITCAEX |
| Cites_doi | 10.1007/978-1-4615-9747-6_6 10.1109/52.43044 10.1145/196244.196356 10.1109/TIM.1985.4315366 10.1109/81.331521 10.1145/157485.165003 10.1109/43.3141 10.1002/cta.4490150204 10.1109/ICCD.1993.393414 10.1109/19.6061 |
| ContentType | Journal Article |
| Copyright | 1999 INIST-CNRS |
| Copyright_xml | – notice: 1999 INIST-CNRS |
| DBID | RIA RIE AAYXX CITATION IQODW |
| DOI | 10.1109/81.780375 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Pascal-Francis |
| DatabaseTitle | CrossRef |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Applied Sciences |
| EndPage | 949 |
| ExternalDocumentID | 1918578 10_1109_81_780375 780375 |
| GroupedDBID | -~X 0R~ 29I 3EH 6IK 85S AAJGR AAWTH ABAZT ABQJQ ABVLG ACIWK ACKIV AGQYO AHBIQ AI. AIBXA ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 EBS EJD HZ~ H~9 ICLAB IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL PZZ RIA RIE RNS VH1 VJK AAYXX CITATION IQODW RIG |
| ID | FETCH-LOGICAL-c235t-478cc77f85d7d9645d01ddf4b241cdc8cf704883dbedfc6b2a967a29223cfa3f3 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 0 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000083260900006&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1057-7122 |
| IngestDate | Mon Jul 21 09:12:40 EDT 2025 Sat Nov 29 01:37:58 EST 2025 Wed Aug 27 02:53:33 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Issue | 8 |
| Keywords | Analog circuit Algorithm Built in self test Computer aided design Fault diagnostic Reengineering |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html CC BY 4.0 |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c235t-478cc77f85d7d9645d01ddf4b241cdc8cf704883dbedfc6b2a967a29223cfa3f3 |
| PageCount | 11 |
| ParticipantIDs | crossref_primary_10_1109_81_780375 pascalfrancis_primary_1918578 ieee_primary_780375 |
| PublicationCentury | 1900 |
| PublicationDate | 1999-08-01 |
| PublicationDateYYYYMMDD | 1999-08-01 |
| PublicationDate_xml | – month: 08 year: 1999 text: 1999-08-01 day: 01 |
| PublicationDecade | 1990 |
| PublicationPlace | New York, NY |
| PublicationPlace_xml | – name: New York, NY |
| PublicationTitle | IEEE transactions on circuits and systems. 1, Fundamental theory and applications |
| PublicationTitleAbbrev | T-CAS1 |
| PublicationYear | 1999 |
| Publisher | IEEE Institute of Electrical and Electronics Engineers |
| Publisher_xml | – name: IEEE – name: Institute of Electrical and Electronics Engineers |
| References | ref12 tomita (ref8) 1994 ref14 wierzba (ref16) 1991 byne (ref1) 1992 ref11 ref10 wey (ref3) 1997 ref2 chung (ref6) 1993 ref7 ref9 wey (ref13) 1987; cas 34 ref4 mitchell (ref5) 1983 huang (ref15) 1998 |
| References_xml | – ident: ref11 doi: 10.1007/978-1-4615-9747-6_6 – year: 1991 ident: ref16 publication-title: Sspice User Manual – ident: ref2 doi: 10.1109/52.43044 – start-page: 212 year: 1994 ident: ref8 article-title: rectification of multiple logic design errors in multiple output circuits publication-title: 31st Design Automation Conference doi: 10.1145/196244.196356 – ident: ref9 doi: 10.1109/TIM.1985.4315366 – ident: ref12 doi: 10.1109/81.331521 – year: 1998 ident: ref15 publication-title: Efficient testing paradigms and diagnosable design methodologies for mixed-signal integrated circuits and systems – start-page: 274 year: 1983 ident: ref5 article-title: an intelligent aid for circuit redesign publication-title: Proc Nat Conf Artificial Intelligence – start-page: 1001 year: 1997 ident: ref3 article-title: development of redesign process for digital vlsi systems publication-title: Proc 40th Midwest Symp Circuits and Systems – start-page: 226 year: 1992 ident: ref1 article-title: a conceptual foundation for software re-engineering publication-title: Proc IEEE Conf on Software Maintenance – start-page: 503 year: 1993 ident: ref6 article-title: diagnosis and correction of logic design errors in digital circuits publication-title: 30th ACM/IEEE Design Automation Conference doi: 10.1145/157485.165003 – ident: ref7 doi: 10.1109/43.3141 – ident: ref14 doi: 10.1002/cta.4490150204 – ident: ref4 doi: 10.1109/ICCD.1993.393414 – ident: ref10 doi: 10.1109/19.6061 – volume: cas 34 start-page: 107 year: 1987 ident: ref13 article-title: a decision process for analog system fault diagnosis publication-title: IEEE Trans IEEE Trans Circuits Syst |
| SSID | ssj0014848 |
| Score | 1.2782431 |
| Snippet | Reengineering of electronic circuits has received considerable interest in the design automation community. Reengineering is the examination and alternation of... |
| SourceID | pascalfrancis crossref ieee |
| SourceType | Index Database Publisher |
| StartPage | 939 |
| SubjectTerms | Analog circuits Applied sciences Built-in self-test Circuit properties Circuit simulation Circuit testing Circuit topology Design automation Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Fault diagnosis Nonlinear circuits Transfer functions |
| Title | Redesignability check for analog circuits with incomplete implementation information |
| URI | https://ieeexplore.ieee.org/document/780375 |
| Volume | 46 |
| WOSCitedRecordID | wos000083260900006&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) issn: 1057-7122 databaseCode: RIE dateStart: 19920101 customDbUrl: isFulltext: true dateEnd: 20031231 titleUrlDefault: https://ieeexplore.ieee.org/ omitProxy: false ssIdentifier: ssj0014848 providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ3dS8MwEMCDDh_0wY-pOHUSxNdu_Uiby6OIwwcZIhP2VtJLAkXsZOsE_3ubpJsb-OJbCD0Idy13vdz9jpA70KBAhCxQSZIEzPYAFxKzQGNRmMYFCpAOmf_Mx2OYTsVLy9l2vTBaa1d8pgd26e7y1QyXNlU25GAntu6SXc4z36q1vjBgwHzXW8oDHsVxCxGKQjGEaOAFt1yPm6ViKyHlolGG8VMsNlzL6Ohfhzomh20ESe-9yU_Ijq665GCDK3hKJq9aucoMD-H-po1l8J028SmVlc3WUCznuCzrBbV5WGoJDZYSXGtafqwKyq3FaMtVtesz8jZ6nDw8Be34hADjJK0DxgGRcwOp4kpkLFVhpJRhReO0USGg4fbzTVShlcGsiKXIuIxFEzCgkYlJzkmnmlX6gtAQm6gwY6A0ZMyiQ1NtJGJj6AxkzKFHbleazT89JSN3fxehyCHKvYp6pGu1t35gtdvfMsGvvLCYKrj8U-qK7Ht-gq3Euyader7UfbKHX3W5mN-4V-MHSy-7Gw |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ3dS8MwEMCDTkF98Fucn0F8rfYjbS6PIoriHCITfCvpJYEidrJ1gv-9vbbTDXzxLYQehLuWu17ufsfYOVgwoHzhmSiKPEE9wJnGxLOYZa5ygQp0jczvyX4fXl_VU8vZrnthrLV18Zm9oGV9l2-GOKFU2aUEmti6yJZocFbbrPVzZSBANH1vsfRkEIYtRijw1SUEF43onPOpp6lQLaQeV-pwzRyLGedyu_GvY22y9TaG5FeN0bfYgi222doMWXCHDZ6tqWszGgz3F69sg2-8ilC5LihfwzEf4SQvx5wysZwYDcQJLi3P36cl5WQz3pJVab3LXm5vBtd3XjtAwcMwiktPSECU0kFspFGJiI0fGONEVrltNAjoJH3AkcmscZhkoVaJ1KGqQgZ0OnLRHusUw8LuM-5jFRcmAoyFRBA8NLZOI1amTkCHErrsbKrZ9KPhZKT1_4WvUgjSRkVdtk3a-3lguns8Z4JfeUWgKjj4U-qUrdwNHntp777_cMhWG5oC1eUdsU45mthjtoyfZT4endSvyTcyEb5k |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Redesignability+check+for+analog+circuits+with+incomplete+implementation+information&rft.jtitle=IEEE+transactions+on+circuits+and+systems.+1%2C+Fundamental+theory+and+applications&rft.au=Chin-Long+Wey&rft.au=Wei-Hsing+Huang&rft.date=1999-08-01&rft.issn=1057-7122&rft.volume=46&rft.issue=8&rft.spage=939&rft.epage=949&rft_id=info:doi/10.1109%2F81.780375&rft.externalDBID=n%2Fa&rft.externalDocID=10_1109_81_780375 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1057-7122&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1057-7122&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1057-7122&client=summon |