HDL-based LDPC-RS encoder-decoder with MEA technique for resilient zedBoard communication
Error correction coding has been integral to digital communications since the introduction of Hamming codes and Reed-Solomon codes, with Low-Density Parity-Check (LDPC) codes later enhancing performance in modern systems. This work presents a hardware-based implementation of a resilient and efficien...
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| Vydáno v: | Engineering Research Express Ročník 7; číslo 4; s. 45237 - 45251 |
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31.12.2025
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| Abstract | Error correction coding has been integral to digital communications since the introduction of Hamming codes and Reed-Solomon codes, with Low-Density Parity-Check (LDPC) codes later enhancing performance in modern systems. This work presents a hardware-based implementation of a resilient and efficient wireless communication system that integrates LDPC and Reed-Solomon (RS) codes for robust error correction. The architecture employs an LDPC (8,7) code as the outer code and an RS (8,2) code as the inner code, with interleaving applied between them to effectively mitigate burst errors and inter-symbol interference (ISI). The RS decoder is implemented using the Modified Euclidean algorithm (MEA), enabling efficient symbol-level error correction with reduced hardware complexity. The entire design is modeled in VHDL and synthesized using the Xilinx Vivado Design Suite for deployment on a Zynq-7000-based ZedBoard FPGA. Wireless transmission is carried out via the HC-12 SI4463 transceiver operating at 433 MHz. Simulation and on-board testing demonstrate that the concatenated LDPC–RS coding approach significantly improves bit error rate (BER) performance under noisy and dispersive channel conditions. The proposed system offers a reliable and resource-optimized solution for embedded wireless applications and FPGA-based communication platforms. |
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| AbstractList | Error correction coding has been integral to digital communications since the introduction of Hamming codes and Reed-Solomon codes, with Low-Density Parity-Check (LDPC) codes later enhancing performance in modern systems. This work presents a hardware-based implementation of a resilient and efficient wireless communication system that integrates LDPC and Reed-Solomon (RS) codes for robust error correction. The architecture employs an LDPC (8,7) code as the outer code and an RS (8,2) code as the inner code, with interleaving applied between them to effectively mitigate burst errors and inter-symbol interference (ISI). The RS decoder is implemented using the Modified Euclidean algorithm (MEA), enabling efficient symbol-level error correction with reduced hardware complexity. The entire design is modeled in VHDL and synthesized using the Xilinx Vivado Design Suite for deployment on a Zynq-7000-based ZedBoard FPGA. Wireless transmission is carried out via the HC-12 SI4463 transceiver operating at 433 MHz. Simulation and on-board testing demonstrate that the concatenated LDPC–RS coding approach significantly improves bit error rate (BER) performance under noisy and dispersive channel conditions. The proposed system offers a reliable and resource-optimized solution for embedded wireless applications and FPGA-based communication platforms. |
| Author | Chauhan, Amit Kr Singh Singh, Aman Pathak, Harsh Singh, Arun Kumar Upadhyay, Ashwini Kumar Verma, Archana |
| Author_xml | – sequence: 1 givenname: Archana orcidid: 0000-0001-7486-6235 surname: Verma fullname: Verma, Archana organization: Rajkiya Engineering College Department of Electronics Engineering, Kannauj, India – sequence: 2 givenname: Arun Kumar surname: Singh fullname: Singh, Arun Kumar organization: Rajkiya Engineering College Department of Electronics Engineering, Kannauj, India – sequence: 3 givenname: Amit Kr Singh surname: Chauhan fullname: Chauhan, Amit Kr Singh organization: Rajkiya Engineering College Department of Electronics Engineering, Kannauj, India – sequence: 4 givenname: Ashwini Kumar surname: Upadhyay fullname: Upadhyay, Ashwini Kumar organization: Rajkiya Engineering College Department of Electronics Engineering, Kannauj, India – sequence: 5 givenname: Aman orcidid: 0009-0006-3852-8945 surname: Singh fullname: Singh, Aman organization: Rajkiya Engineering College Department of Electronics Engineering, Kannauj, India – sequence: 6 givenname: Harsh surname: Pathak fullname: Pathak, Harsh organization: Rajkiya Engineering College Department of Electronics Engineering, Kannauj, India |
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| SubjectTerms | encoder-decoder architecture error correction low-density parity-check (LDPC) codes modified euclidean algorithm (MEA) |
| Title | HDL-based LDPC-RS encoder-decoder with MEA technique for resilient zedBoard communication |
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