Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification

The use of formal models to describe early versions of the structure and the behavior of a system has become common practice in industry. UML and OCL are the de-facto specification languages for these tasks. They allow for capturing system properties and module behavior in an abstract but still form...

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Bibliographic Details
Published in:	IEEE transactions on computer-aided design of integrated circuits and systems Vol. 36; no. 3; pp. 475 - 488
Main Authors:	Gonzalez-de-Aledo, Pablo, Przigoda, Nils, Wille, Robert, Drechsler, Rolf, Sanchez, Pablo
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.03.2017 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	C++ languages C/C++/SystemC Computational modeling Context Design Formal method Formal specifications Integrated circuit modeling model checking SAT/SMT solvers Solid modeling Specification and description languages Switches symbolic execution UML/OCL Unified modeling language Verification
ISSN:	0278-0070, 1937-4151
Online Access:	Get full text
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