APA (7th ed.) Citation

Gonzalez-de-Aledo, P., Przigoda, N., Wille, R., Drechsler, R., & Sanchez, P. (2017). Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. IEEE transactions on computer-aided design of integrated circuits and systems, 36(3), 475-488. https://doi.org/10.1109/TCAD.2016.2611494

Chicago Style (17th ed.) Citation

Gonzalez-de-Aledo, Pablo, Nils Przigoda, Robert Wille, Rolf Drechsler, and Pablo Sanchez. "Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 36, no. 3 (2017): 475-488. https://doi.org/10.1109/TCAD.2016.2611494.

MLA (9th ed.) Citation

Gonzalez-de-Aledo, Pablo, et al. "Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 36, no. 3, 2017, pp. 475-488, https://doi.org/10.1109/TCAD.2016.2611494.