An FPGA-based efficient accelerator for fault interaction of rupture dynamics

Efficiently predicting aftershocks based on rupture dynamics simulation is a crucial task in high-performance computing, traditionally dependent on supercomputers. However, the constraints of power supply makes supercomputers impractical right after a primary earthquake event. This positions FPGAs,...

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Vydáno v:The Journal of supercomputing Ročník 81; číslo 14; s. 1323
Hlavní autoři: Yuan, Ming, Liu, Qiang, Gan, Lin
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York Springer Nature B.V 10.09.2025
Témata:
Aftershocks
Algorithms
Central processing units
CPUs
Earthquake prediction
Earthquakes
Energy efficiency
Fault lines
Field programmable gate arrays
High performance computing
Parallel processing
Power efficiency
Simulation
Supercomputers
Trends
ISSN:1573-0484, 0920-8542, 1573-0484
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Shrnutí:Efficiently predicting aftershocks based on rupture dynamics simulation is a crucial task in high-performance computing, traditionally dependent on supercomputers. However, the constraints of power supply makes supercomputers impractical right after a primary earthquake event. This positions FPGAs, known for their high power efficiency and reconfigurability, as a highly promising alternative. Within rupture dynamics simulation, fault interaction is the most computationally intensive component, making its acceleration crucial for enhancing overall performance. By thoroughly considering both the computational characteristics of fault interaction and the reconfigurable capabilities of FPGAs, we have devised a high-performance, power-efficient accelerator for fault interaction. On one hand, we conduct an in-depth analysis of the algorithm’s data dependencies and exploit parallelization at multiple levels to maximize performance. On the other hand, we propose novel dataflow optimizations, such as prefetching and overlapping computations across different stages, to further enhance efficiency. Additionally, we implement a latency-matching strategy and a flag-based mechanism to ensure seamless coordination between computational stages. Experimental results demonstrate the superior efficiency of our FPGA accelerator across geological models. Against a 12-core Intel Xeon CPU, the FPGA achieves 12.3× speedup and 27.1× energy efficiency for the uniform Basin Model, delivering 1.8× the energy efficiency of the contemporary RTX 2080 GPU. For the irregular Mountain Model, it delivers 15.4× speedup and 35.8× energy efficiency over the same CPU, exceeding the RTX 4080 by 5.0× in efficiency while approaching its computational throughput.
Bibliografie:ObjectType-Article-1
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ISSN:1573-0484
0920-8542
1573-0484
DOI:10.1007/s11227-025-07801-x