Model-based Design of a High-Throughput Canny Edge Detection Accelerator on Zynq-7000 FPGA

This paper presents a novel approach for fast FPGA prototyping of the Canny edge detection algorithm using High-Level Synthesis (HLS) based on the HDL Coder. Traditional RTL-based design methodologies for implementing image processing algorithms on FPGAs can be time-consuming and error-prone. HLS of...

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Vydané v:	Engineering, technology & applied science research Ročník 14; číslo 2; s. 13547 - 13553
Hlavní autori:	Alhomoud, Ahmed, Ghodhbani, Refka, Saidani, Taoufik, Zayani, Hafedh Mahmoud, Said, Yahia, Ammar, Mohamed Ben, Slimane, Jihane Ben
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	01.04.2024
ISSN:	2241-4487, 1792-8036
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Popis
Shrnutí:	This paper presents a novel approach for fast FPGA prototyping of the Canny edge detection algorithm using High-Level Synthesis (HLS) based on the HDL Coder. Traditional RTL-based design methodologies for implementing image processing algorithms on FPGAs can be time-consuming and error-prone. HLS offers a higher level of abstraction, enabling designers to focus on algorithmic functionality while the tool automatically generates efficient hardware descriptions. This advantage was exploited by implementing the Canny edge detection algorithm in MATLAB/Simulink and utilizing the HDL Coder to automatically convert it into synthesizable VHDL code. This design flow significantly reduces development time and complexity compared to the traditional RTL approach. The experimental results showed that the HLS-based Canny edge detector achieved real-time performance on a Xilinx FPGA platform, showcasing the effectiveness of the proposed approach for fast FPGA prototyping in image processing applications.
ISSN:	2241-4487 1792-8036
DOI:	10.48084/etasr.7081